FDB045AN08A0 N-Channel PowerTrench® MOSFET 75 V, 80 A, 4.5 mΩ Features Applications • RDS(on) = 3.9 mΩ ( Typ.) @ VGS = 10 V, ID = 80 A • Synchronous Rectification for ATX / Server / Telecom PSU • QG(tot) = 92 nC ( Typ.
Device Marking FDB045AN08A0 Device FDB045AN08A0 Package D2-PAK Reel Size 330 mm Tape Width 24 mm Quantity 800 units Electrical Characteristics TC = 25°C unless otherwise noted Symbol Parameter Test Conditions Min Typ Max Units 75 - - - V - 1 - - 250 VGS = ±20V - - ±100 nA VGS = VDS, ID = 250μA 2 - 4 V ID = 80A, VGS = 10V - 0.0039 0.0045 ID = 37A, VGS = 6V - 0.0056 0.0084 ID = 80A, VGS = 10V, TJ = 175oC - 0.008 0.
POWER DISSIPATION MULTIPLIER 1.2 200 CURRENT LIMITED BY PACKAGE ID, DRAIN CURRENT (A) 1.0 0.8 0.6 0.4 160 120 80 40 0.2 0 0 25 50 75 100 150 125 0 175 25 50 75 TC , CASE TEMPERATURE (oC) 100 125 150 175 TC, CASE TEMPERATURE (oC) Figure 1. Normalized Power Dissipation vs Ambient Temperature Figure 2. Maximum Continuous Drain Current vs Case Temperature 2 ZθJC, NORMALIZED THERMAL IMPEDANCE 1 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM 0.
2000 500 10μs 1000 100 IAS, AVALANCHE CURRENT (A) ID, DRAIN CURRENT (A) 100μs 1ms 10ms 10 OPERATION N IN THI AREA MAY BE LIMITED BY rDS(ON) 1 DC SINGLE PULSE TJ = MAX RATED TC = 25oC 0.1 0.1 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) STARTING TJ = 150oC 150 VGS = 7V VGS = 10V 120 TJ = 175oC 60 TJ = -55oC VGS = 6V 90 60 VGS = 5V TC = 25oC PULSE DURATION = 80μs DUTY CYCLE = 0.5% MAX 30 0 4.0 100 Figure 6. Unclamped Inductive Switching Capability 30 0 4.5 5.0 5.
1.2 1.15 ID = 250μA NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE NORMALIZED GATE THRESHOLD VOLTAGE VGS = VDS, ID = 250μA 1.0 0.8 0.6 0.4 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC) 1.00 0.95 -40 0 40 80 120 160 200 TJ , JUNCTION TEMPERATURE (oC) Figure 12. Normalized Drain to Source Breakdown Voltage vs Junction Temperature 10000 VGS , GATE TO SOURCE VOLTAGE (V) 10 CISS = CGS + CGD C, CAPACITANCE (pF) 1.05 0.90 -80 200 Figure 11.
VDS BVDSS tP L VARY tP TO OBTAIN REQUIRED PEAK IAS + RG - VGS VDS IAS VDD VDD DUT tP 0V IAS 0 0.01Ω tAV Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms VDS VDD Qg(TOT) VDS L VGS + - VGS VGS = 10V Qgs2 VDD DUT VGS = 2V Ig(REF) 0 Qg(TH) Qgs Qgd Ig(REF) 0 Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms VDS tON tOFF td(ON) td(OFF) RL tr VDS 90% - VDD 10% 0 10% DUT 90% VGS VGS 0 Figure 19.
The maximum rated junction temperature, TJM , and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM , in an application. Therefore the application’s ambient temperature, TA (oC), and thermal resistance RθJA (oC/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part. RθJA = 26.51+ 19.84/(0.262+Area) EQ.2 RθJA = 26.
.SUBCKT FDB045AN08A0 2 1 3 ; CA 12 8 1.5e-9 CB 15 14 1.5e-9 CIN 6 8 6.4e-9 rev March 2002 DRAIN 2 5 10 DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD ESLC GATE 1 LDRAIN 2 5 1e-9 LGATE 1 9 4.81e-9 LSOURCE 3 7 4.63e-9 11 + 17 EBREAK 18 - 50 RDRAIN 6 8 + LGATE DBREAK + 5 51 ESG RLDRAIN RSLC1 51 RSLC2 EBREAK 11 7 17 18 82.
REV March 2002 template FDB045AN08A0 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl = 2.4e-11, n1 = 1.04, rs = 1.76e-3, trs1 = 2.7e-3, trs2 = 2e-7, xti = 3.9, cjo = 4.35e-9, tt = 1e-8, m = 5.4e-1) dp..model dbreakmod = (rs = 1.5e-1, trs1 = 1e-3, trs2 = -8.9e-6) dp..model dplcapmod = (cjo = 1.35e-9, isl =10e-30, nl =10, m = 0.53) m..model mmedmod = (type=_n, vto = 3.7, kp = 9, is =1e-30, tox=1) m..model mstrongmod = (type=_n, vto = 4.4, kp = 250, is = 1e-30, tox = 1) m..
th REV 23 March 2002 JUNCTION FDB045AN08A0T CTHERM1 th 6 6.45e-3 CTHERM2 6 5 3e-2 CTHERM3 5 4 1.4e-2 CTHERM4 4 3 1.65e-2 CTHERM5 3 2 4.85e-2 CTHERM6 2 tl 1e-1 RTHERM1 CTHERM1 6 RTHERM1 th 6 3.24e-3 RTHERM2 6 5 8.08e-3 RTHERM3 5 4 2.28e-2 RTHERM4 4 3 1e-1 RTHERM5 3 2 1.1e-1 RTHERM6 2 tl 1.4e-1 RTHERM2 CTHERM2 5 SABER Thermal Model SABER thermal model FDB045AN08A0T template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 = 6.45e-3 ctherm.ctherm2 6 5 = 3e-2 ctherm.ctherm3 5 4 = 1.
FDB045AN08A0 — N-Channel PowerTrench® MOSFET Mechanical Dimensions TO-263 2L (D2PAK) Figure 22. 2LD, TO263, Surface Mount Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
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