FDP050AN06A0 / FDB050AN06A0 N-Channel PowerTrench® MOSFET 60 V, 80 A, 5 mΩ Features Applications • RDS(on) = 4.3 mΩ ( Typ.) @ VGS = 10 V, ID = 80 A • Synchronous Rectification for ATX / Server / Telecom PSU • QG(tot) = 61 nC ( Typ.
Device Marking FDB050AN06A0 Device FDB050AN06A0 Package D2-PAK Reel Size 330 mm Tape Width 24 mm Quantity 800 units FDP050AN06A0 FDP050AN06A0 TO-220 Tube N/A 50 units Electrical Characteristics TC = 25°C unless otherwise noted Symbol Parameter Test Conditions Min Typ Max Unit V Off Characteristics B VDSS Drain to Source Breakdown Voltage IDSS Zero Gate Voltage Drain Current IGSS Gate to Source Leakage Current ID = 250µA, VGS = 0V 60 - - - - 1 - - 250 VGS = ±20V - - ±10
1.2 160 CURRENT LIMITED BY PACKAGE ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER 1.0 0.8 0.6 0.4 120 80 40 0.2 0 0 0 25 50 75 100 150 125 175 25 50 75 TC , CASE TEMPERATURE (o C) 100 125 TC, CASE TEMPERATURE Figure 1. Normalized Power Dissipation vs Ambient Temperature 150 175 (oC) Figure 2. Maximum Continuous Drain Current vs Case Temperature 2 ZθJC, NORMALIZED THERMAL IMPEDANCE 1 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM 0.
1000 500 If R = 0 tAV = (L)(I AS)/(1.3*RATED BVDSS - VDD) If R ≠ 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] IAS, AVALANCHE CURRENT (A) 10µs ID, DRAIN CURRENT (A) 100µs 100 1ms OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 10 10ms DC 1 SINGLE PULSE TJ = MAX RATED TC = 25oC 100 STARTING TJ = 25oC 10 STARTING TJ = 150 oC 1 0.01 0.1 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 100 160 PULSE DURATION = 80µs DUTY CYCLE = 0.
1.4 1.15 ID = 250µA NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE VGS = VDS, ID = 250µA NORMALIZED GATE THRESHOLD VOLTAGE 1.2 1.0 0.8 0.6 0.4 -80 -40 0 40 80 120 TJ, JUNCTION TEMPERATURE 160 1.00 0.95 0.90 -80 200 -40 0 40 80 120 160 TJ , JUNCTION TEMPERATURE (oC) 200 Figure 12. Normalized Drain to Source Breakdown Voltage vs Junction Temperature 10000 10 VGS , GATE TO SOURCE VOLTAGE (V) CISS = CGS + CGD C, CAPACITANCE (pF) 1.05 (oC) Figure 11.
VDS BVDSS tP L VDS VARY tP TO OBTAIN REQUIRED PEAK IAS IAS + RG VDD VDD - VGS DUT tP IAS 0V 0 0.01Ω tAV Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms VDS VDD Qg(TOT) VDS L VGS VGS VGS = 10V + Qgs2 VDD DUT VGS = 2V Ig(REF) 0 Qg(TH) Qgs Qgd Ig(REF) 0 Figure 18. Gate Charge Waveforms Figure 17. Gate Charge Test Circuit VDS tON tOFF td(ON) td(OFF) RL tr VDS tf 90% 90% + VGS VDD - 10% 0 10% DUT 90% RGS VGS VGS 0 Figure 19.
The maximum rated junction temperature, TJM , and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM , in an application. Therefore the application’s ambient temperature, TA (oC), and thermal resistance RθJA (oC/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part. RθJA = 26.51+ 19.84/(0.262+Area) EQ.2 RθJA = 26.
.SUBCKT FDB050AN06A0 2 1 3 ; rev February 2003 Ca 12 8 1.5e-9 Cb 15 14 1.5e-9 Cin 6 8 3.75e-9 LDRAIN DPLCAP 10 Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD Dplcap 10 5 DplcapMOD RLDRAIN RSLC1 51 5 51 ESLC EVTHRES + 19 8 + LGATE GATE 1 11 50 RDRAIN 6 8 ESG DBREAK + RSLC2 Ebreak 11 7 17 18 64.
rev February 2003 template FDB050AN06A0 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl=1.3e-11,nl=1.04,rs=1.76e-3,trs1=2.7e-3,trs2=2e-7,cjo=2.7e-9,m=5.4e-1,tt=1e-10,xti=3.9) dp..model dbreakmod = (rs=8e-1,trs1=5e-4,trs2=-8.9e-6) dp..model dplcapmod = (cjo=1.3e-9,isl=10e-30,nl=10,m=0.45) m..model mmedmod = (type=_n,vto=3.7,kp=9,is=1e-30, tox=1) m..model mstrongmod = (type=_n,vto=4.29,kp=155,is=1e-30, tox=1) m..model mweakmod = (type=_n,vto=3.05,kp=0.03,is=1e-30, tox=1,rs=0.
th JUNCTION REV 23 February 2003 FDB050AN06A0T CTHERM1 TH 6 5e-3 CTHERM2 6 5 1.3e-2 CTHERM3 5 4 1.4e-2 CTHERM4 4 3 1.9e-2 CTHERM5 3 2 4.7e-2 CTHERM6 2 TL 9e-2 RTHERM1 CTHERM1 6 RTHERM1 TH 6 1e-2 RTHERM2 6 5 3.1e-2 RTHERM3 5 4 4.5e-2 RTHERM4 4 3 1.2e-1 RTHERM5 3 2 1.3e-1 RTHERM6 2 TL 1.52e-1 RTHERM2 CTHERM2 5 SABER Thermal Model SABER thermal model FDB050AN06A0T template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 =5e-3 ctherm.ctherm2 6 5 =1.3e-2 ctherm.ctherm3 5 4 =1.4e-2 ctherm.
FDP050AN06A0 / FDB050AN06A0 — N-Channel PowerTrench® MOSFET Mechanical Dimensions TO-220 3L Figure 22. TO-220, Molded, 3Lead, Jedec Variation AB Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
FDP050AN06A0 / FDB050AN06A0 — N-Channel PowerTrench® MOSFET Mechanical Dimensions TO-263 2L (D2PAK) Figure 23. 2LD, TO263, Surface Mount Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
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