FDP060AN08A0 / FDB060AN08A0 N-Channel PowerTrench® MOSFET 75 V, 80 A, 6 mΩ Features Applications • RDS(on) = 4.8 mΩ ( Typ.) @ VGS = 10 V, ID = 80 A • Synchronous Rectification for ATX / Server / Telecom PSU • QG(tot) = 73 nC ( Typ.
Device Marking FDB060AN08A0 Device FDB060AN08A0 Package D2-PAK Reel Size 330 mm Tape Width 24 mm Quantity 800 units FDP060AN08A0 FDP060AN08A0 TO-220 Tube N/A 50 units Electrical Characteristics TC = 25°C unless otherwise noted Symbol Parameter Test Conditions Min Typ Max Unit V Off Characteristics B VDSS Drain to Source Breakdown Voltage IDSS Zero Gate Voltage Drain Current IGSS Gate to Source Leakage Current ID = 250µA, VGS = 0V 75 - - - - 1 - - 250 VGS = ±20V - - ±10
150 1.0 125 ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER 1.2 0.8 0.6 0.4 0.2 CURRENT LIMITED BY PACKAGE 100 75 50 25 0 0 25 50 75 100 150 125 0 175 25 50 TC , CASE TEMPERATURE (o C) ZθJC, NORMALIZED THERMAL IMPEDANCE 1 100 125 TC, CASE TEMPERATURE Figure 1. Normalized Power Dissipation vs Ambient Temperature 2 75 150 175 (oC) Figure 2. Maximum Continuous Drain Current vs Case Temperature DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM 0.
1000 500 If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R ≠ 0 tAV = (L/R)ln[(I AS*R)/(1.3*RATED BVDSS - VDD) +1] IAS, AVALANCHE CURRENT (A) ID, DRAIN CURRENT (A) 10µs 100µs 100 1ms OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 10 10ms DC 1 SINGLE PULSE TJ = MAX RATED TC = 25oC 100 STARTING TJ = 25oC 10 STARTING TJ = 150oC 0.1 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 1 0.01 100 Figure 5.
1.2 VGS = VDS, ID = 250µA NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE NORMALIZED GATE THRESHOLD VOLTAGE 1.2 1.0 0.8 0.6 0.4 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC) 1.0 10 VGS , GATE TO SOURCE VOLTAGE (V) CISS = CGS + CGD COSS ≅ CDS + C GD CRSS = CGD VGS = 0V, f = 1MHz 100 0.
VDS BVDSS tP L VARY tP TO OBTAIN REQUIRED PEAK IAS + RG - VGS VDS IAS VDD VDD DUT tP 0V IAS 0 0.01Ω tAV Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms VDS VDD Qg(TOT) VDS L VGS + - VGS VGS = 10V Qgs2 VDD DUT VGS = 2V Ig(REF) 0 Qg(TH) Qgs Qgd Ig(REF) 0 Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms VDS tON tOFF td(ON) td(OFF) RL tr VDS 90% - VDD 10% 0 10% DUT 90% VGS VGS 0 Figure 19.
The maximum rated junction temperature, TJM , and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM , in an application. Therefore the application’s ambient temperature, TA (oC), and thermal resistance RθJA (oC/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part. RθJA = 26.51+ 19.84/(0.262+Area) EQ.2 RθJA = 26.
.SUBCKT FDP060AN08A0 2 1 3 ; rev October 2002 Ca 12 8 2.5e-9 Cb 15 14 2.1e-9 Cin 6 8 4.7e-9 DPLCAP 10 RSLC2 + GATE 1 Lgate 1 9 5.3e-9 Ldrain 2 5 1.0e-9 Lsource 3 7 5e-9 RLGATE EVTEMP RGATE + 18 22 9 20 ESLC 11 + 17 EBREAK 18 - 50 EVTHRES + 19 8 6 21 16 DBODY MWEAK MMED MSTRO CIN LSOURCE 8 7 RSOURCE RLgate 1 9 53 RLdrain 2 5 10 RLsource 3 7 50 Mmed 16 6 8 8 MmedMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD DBREAK RDRAIN 6 8 ESG LGATE 5 51 - Ebreak 11 7 17 18 82.
rev October 2002 template FDP060AN08A0 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl=2e-11,nl=1.04,rs=1.76e-3,trs1=2.7e-3,trs2=1e-6,cjo=3.2e-9,m=5.6e-1,tt=3e-10,xti=3.9) dp..model dbreakmod = (rs=3e-1,trs1=1e-3,trs2=-8.9e-6) dp..model dplcapmod = (cjo=1.56e-9,isl=10e-30,nl=10,m=0.53) m..model mmedmod = (type=_n,vto=3.6,kp=6,is=1e-30, tox=1) m..model mstrongmod = (type=_n,vto=4.22,kp=220,is=1e-30, tox=1) m..model mweakmod = (type=_n,vto=3,kp=0.03,is=1e-30, tox=1,rs=0.1) LDRAIN sw_vcsp..
th JUNCTION REV 23 October 2002 FDP060AN08A0T CTHERM1 TH 6 9.6e-3 CTHERM2 6 5 9.7e-3 CTHERM3 5 4 9.8e-3 CTHERM4 4 3 1e-2 CTHERM5 3 2 3e-2 CTHERM6 2 TL 9e-2 RTHERM1 CTHERM1 6 RTHERM1 TH 6 3.2e-3 RTHERM2 6 5 8.1e-3 RTHERM3 5 4 2.3e-2 RTHERM4 4 3 1.2e-1 RTHERM5 3 2 1.5e-1 RTHERM6 2 TL 1.6e-1 RTHERM2 CTHERM2 5 SABER Thermal Model SABER thermal model FDP060AN08A0T template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 =9.6e-3 ctherm.ctherm2 6 5 =9.7e-3 ctherm.ctherm3 5 4 =9.8e-3 ctherm.
FDP060AN08A0 / FDB060AN08A0 — N-Channel PowerTrench® MOSFET Mechanical Dimensions TO-220 3L Figure 22. TO-220, Molded, 3Lead, Jedec Variation AB Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
FDP060AN08A0 / FDB060AN08A0 — N-Channel PowerTrench® MOSFET Mechanical Dimensions TO-263 2L (D2PAK) Figure 23. 2LD, TO263, Surface Mount Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
