FDB13AN06A0 N-Channel PowerTrench® MOSFET 60 V, 62 A, 13.5 mΩ Features Applications • rDS(on) = 11.5 mΩ ( Typ.) @ VGS = 10 V, ID = 62 A • Motor Load Control • Qg(tot) = 22 nC ( Typ.
Device Marking FDB13AN06A0 Device FDB13AN06A0 Package D2-PAK Reel Size 330 mm Tape Width 24 mm Quantity 800 units Electrical Characteristics TC = 25°C unless otherwise noted Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage IDSS Zero Gate Voltage Drain Current IGSS Gate to Source Leakage Current ID = 250µA, VGS = 0V 60 - - V - - 1 - - 250 µA VGS = ±20V - - ±100 nA - 4 V V DS = 50V VGS = 0V TC = 150oC On Cha
1.2 80 ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER 1.0 0.8 0.6 0.4 60 40 20 0.2 0 0 25 50 75 100 150 125 0 175 25 50 75 TC , CASE TEMPERATURE (oC) 100 125 150 175 TC, CASE TEMPERATURE (oC) Figure 1. Normalized Power Dissipation vs Ambient Temperature Figure 2. Maximum Continuous Drain Current vs Case Temperature 2 ZθJC, NORMALIZED THERMAL IMPEDANCE 1 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM 0.
100 1000 If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R ≠ 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] 100 100µs 1ms OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 10 1 0.1 IAS, AVALANCHE CURRENT (A) ID, DRAIN CURRENT (A) 10µs SINGLE PULSE TJ = MAX RATED TC = 25oC 10ms DC 10 STARTING TJ = 150oC 1 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 100 0.01 0.1 1 10 tAV, TIME IN AVALANCHE (ms) 100 NOTE: Refer to Fairchild Application Notes AN7514 and AN7515 Figure 5.
1.4 1.2 ID = 250µA NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE VGS = VDS, I D = 250µA NORMALIZED GATE THRESHOLD VOLTAGE 1.2 1.0 0.8 0.6 0.4 -80 -40 0 40 80 120 160 1.1 1.0 0.9 200 -80 -40 TJ, JUNCTION TEMPERATURE (oC) Figure 11. Normalized Gate Threshold Voltage vs Junction Temperature 40 80 120 160 200 Figure 12.
VDS BVDSS tP L VARY tP TO OBTAIN REQUIRED PEAK IAS + RG - VGS VDS IAS VDD VDD DUT tP 0V IAS 0 0.01Ω tAV Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms VDS VDD Qg(TOT) VDS L VGS + - VGS VGS = 10V Qgs2 VDD DUT VGS = 2V Ig(REF) 0 Qg(TH) Qgs Qgd Ig(REF) 0 Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms VDS tON tOFF td(ON) td(OFF) RL tr VDS 90% - VDD 10% 0 10% DUT 90% VGS VGS 0 Figure 19.
The maximum rated junction temperature, TJM , and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM , in an application. Therefore the application’s ambient temperature, TA (oC), and thermal resistance RθJA (oC/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part. RθJA = 26.51+ 19.84/(0.262+Area) EQ.2 RθJA = 26.
.SUBCKT FDB13AN06A0 2 1 3 ; rev August 2002 Ca 12 8 5.1e-10 Cb 15 14 5.1e-10 Cin 6 8 1.3e-9 LDRAIN DPLCAP 10 Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD Dplcap 10 5 DplcapMOD RLDRAIN RSLC1 51 5 51 ESLC EVTHRES + 19 8 + LGATE GATE 1 11 + 17 EBREAK 18 - 50 RDRAIN 6 8 ESG DBREAK + RSLC2 Ebreak 11 7 17 18 65.
rev August 2002 template FDB13AN06A0 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl=1.5e-11,nl=1.08,rs=3.3e-3,trs1=2.2e-3,trs2=2.5e-9,cjo=0.9e-9,m=5.1e-1,tt=1e-9,xti=3.9) dp..model dbreakmod = (rs=1.5e-1,trs1=1e-3,trs2=-8.9e-6) dp..model dplcapmod = (cjo=4.1e-10,isl=10e-30,nl=10,m=0.45) m..model mmedmod = (type=_n,vto=3.5,kp=6,is=1e-30, tox=1) m..model mstrongmod = (type=_n,vto=4.3,kp=50,is=1e-30, tox=1) m..model mweakmod = (type=_n,vto=2.88,kp=0.05,is=1e-30, tox=1,rs=0.
th JUNCTION REV 23 March 2002 FDB13AN06A0T CTHERM1 TH 6 9.7e-4 CTHERM2 6 5 6.2e-3 CTHERM3 5 4 4.6e-3 CTHERM4 4 3 4.9e-3 CTHERM5 3 2 8e-3 CTHERM6 2 TL 4.2e-2 RTHERM1 RTHERM1 TH 6 5.24e-2 RTHERM2 6 5 10.08e-2 RTHERM3 5 4 4.28e-1 RTHERM4 4 3 1.8e-1 RTHERM5 3 2 1.9e-1 RTHERM6 2 TL 2.1e-1 CTHERM1 6 RTHERM2 SABER Thermal Model CTHERM2 5 SABER thermal model FDB14AN06A0T template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 =9.7e-4 ctherm.ctherm2 6 5 =6.2e-3 ctherm.ctherm3 5 4 =4.
FDB13AN06A0 — N-Channel PowerTrench® MOSFET Mechanical Dimensions Figure 22. TO263 (D2PAK), Molded, 2-Lead, Surface Mount Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
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