Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFDB14AN06LA0_F085, MOSFET

FDB14AN06LA0_F085

Rev. C

N-Channel PowerTrench

MOSFET

60V, 60A, 14.6mΩ

Features

• r

DS(ON)

= 12.8mΩ (Typ.), V

= 5V, I

= 60A

• Q

(tot) = 24nC (Typ.), V

= 5V

• Low Miller Charge

• Low Q

Body Diode

• UIS Capability (Single Pulse and Repetitive Pulse)

• Qualified to AEC Q101

Formerly developmental type 83557

Applications

• Motor / Body Load Control

• ABS Systems

• Powertrain Management

• Injection Systems

• DC-DC converters and Off-line UPS

• Distributed Power Architectures and VRMs

• Primary Switch for 12V and 24V systems

MOSFET Maximum Ratings T

= 25°C unless otherwise noted

Thermal Characteristics

This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a

copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/

Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html.

All Fairchild Semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems

certification.

Symbol Parameter Ratings Units

DSS

Drain to Source Voltage 60 V

Gate to Source Voltage ±20 V

Drain Current

67 A

Continuous (T

= 25

C, V

= 10V)

Continuous (T

= 25

C, V

= 5V) 60 A

Continuous (T

= 25

C, V

= 5V, R

θJA

= 43

C/W) 10 A

Pulsed Figure 4 A

Single Pulse Avalanche Energy (Note 1) 46 mJ

Power dissipation 125 W

Derate above 25

C 0.83 W/

, T

STG

Operating and Storage Temperature -55 to 175

θJC

C/W

θJA

Maximum Thermal Resistance Junction to Ambient TO-263, 1in

C/W

TO-263AB

FDB SERIES

GATE

SOURCE

DRAIN

(FLANGE)

December 2010

FDB14AN06LA0_F085

• RoHS Compliant

FDB14AN06LA0_F085 N-Channel PowerTrench

MOSFET

Maximum Thermal Resistance Junction to Case TO-263 1.2

copper pad area

Summary of content (11 pages)

PAGE 1
FDB14AN06LA0_F085 N-Channel PowerTrench® MOSFET 60V, 60A, 14.6mΩ Features Applications • r DS(ON) = 12.8mΩ (Typ.), VGS = 5V, ID = 60A • Motor / Body Load Control • Qg(tot) = 24nC (Typ.
PAGE 2
Device Marking FDB14AN06LA0 Device FDB14AN06LA0_F085 Package TO-263AB Reel Size 330mm Tape Width 24mm Quantity 800 units Electrical Characteristics TC = 25°C unless otherwise noted Symbol Parameter Test Conditions Min Typ Max Units V Off Characteristics BVDSS Drain to Source Breakdown Voltage IDSS Zero Gate Voltage Drain Current IGSS Gate to Source Leakage Current ID = 250µA, VGS = 0V 60 - - - - 1 - - 250 VGS = ±20V - - ±100 nA - 3 V VDS = 50V VGS = 0V TC = 150oC µA
PAGE 3
1.2 80 VGS = 10V ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER 1.0 0.8 0.6 0.4 60 VGS = 5V 40 20 0.2 0 0 25 50 75 100 150 125 0 175 25 50 75 TC , CASE TEMPERATURE (oC) 100 125 150 175 TC, CASE TEMPERATURE (oC) Figure 1. Normalized Power Dissipation vs Ambient Temperature Figure 2. Maximum Continuous Drain Current vs Case Temperature 2 ZθJC, NORMALIZED THERMAL IMPEDANCE 1 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM 0.
PAGE 4
500 1000 If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R ≠ 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] IAS, AVALANCHE CURRENT (A) ID, DRAIN CURRENT (A) 10µs 100 100µs 1ms 10 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 10ms DC 1 SINGLE PULSE TJ = MAX RATED TC = 25o C 100 STARTING TJ = 25o C 10 STARTING TJ = 150oC 1 0.1 1 10 0.001 100 0.01 VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 5. Forward Bias Safe Operating Area 1 10 Figure 6.
PAGE 5
1.4 1.2 ID = 250µA NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE VGS = VDS, ID = 250µA NORMALIZED GATE THRESHOLD VOLTAGE 1.2 1.0 0.8 0.6 0.4 0.2 1.1 1.0 0.9 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (o C) 200 Figure 11. Normalized Gate Threshold Voltage vs Junction Temperature -80 -40 0 40 80 120 160 TJ , JUNCTION TEMPERATURE (oC) 200 Figure 12.
PAGE 6
VDS BVDSS tP L VDS VARY tP TO OBTAIN IAS + RG REQUIRED PEAK IAS VDD VDD - VGS DUT tP IAS 0V 0 0.01Ω tAV Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms VDS VDD Qg(TOT) VDS L VGS VGS VGS = 5V + Qgs2 VDD DUT VGS = 1V Ig(REF) 0 Qg(TH) Qgs Qgd Ig(REF) 0 Figure 17. Gate Charge Test Circuit Figure 18.
PAGE 7
(T –T ) JM A P D M = ----------------------------R θ JA (EQ. 1) In using surface mount devices such as the TO-263 package, the environment in which it is applied will have a significant influence on the part’s current and maximum power dissipation ratings. Precise determination of P DM is complex and influenced by many factors: 1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 80 RθJA = 26.51+ 19.84/(0.262+Area) EQ.2 RθJA = 26.
PAGE 8
.SUBCKT FDP14AN06LA0 2 1 3 ; Ca 12 8 1.8e-9 Cb 15 14 1.8e-9 Cin 6 8 3e-9 rev January 2004 LDRAIN DPLCAP 10 Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD Dplcap 10 5 DplcapMOD RLDRAIN RSLC1 51 5 51 ESLC EVTHRES + 19 8 + LGATE GATE 1 11 + 17 EBREAK 18 - 50 RDRAIN 6 8 ESG DBREAK + RSLC2 Ebreak 11 7 17 18 64.8 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1 It 8 17 1 DRAIN 2 5 EVTEMP RGATE + 18 22 9 20 21 16 DBODY MWEAK 6 MMED MSTRO RLGATE Lgate 1 9 7.
PAGE 9
REV January 2004 template FDP14AN06LA0 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl=1.7e-11,rs=2.8e-3,nl=1.05,trs1=1.5e-3,trs2=1e-6,cjo=1e-9,tt=1.9e-8,m=0.58,ikf=15.00,xti=3) dp..model dbreakmod = (rs=1e-1,trs1=1.12e-3,trs2=1.25e-6) dp..model dplcapmod = (cjo=8e-10,isl=10e-30,nl=10,m=0.57) m..model mmedmod = (type=_n,vto=1.96,kp=8,is=1e-30, tox=1) m..model mstrongmod = (type=_n,vto=2.42,kp=105,is=1e-30, tox=1) m..model mweakmod = (type=_n,vto=1.6,kp=0.04,is=1e-30, tox=1,rs=0.
PAGE 10
th JUNCTION REV January 2004 FDP14AN06LA0T CTHERM1 TH 6 2.5e-3 CTHERM2 6 5 3e-3 CTHERM3 5 4 4e-3 CTHERM4 4 3 7e-3 CTHERM5 3 2 8.2e-3 CTHERM6 2 TL 5e-2 RTHERM1 CTHERM1 6 RTHERM1 TH 6 4.2e-2 RTHERM2 6 5 8.4e-2 RTHERM3 5 4 1.04e-1 RTHERM4 4 3 1.14e-1 RTHERM5 3 2 2.74e-1 RTHERM6 2 TL 3.44e-1 RTHERM2 CTHERM2 5 SABER Thermal Model SABER thermal model FDP14AN06LA0T template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 =2.5e-3 ctherm.ctherm2 6 5 =3e-3 ctherm.ctherm3 5 4 =4e-3 ctherm.
PAGE 11
tm tm tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.