Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFDB15N50, MOSFET

November 2013

FDB15N50 — N-Channel UniFET

MOSFET

FDB15N50 Rev. C1

www.fairchildsemi.com

FDB15N50

N-Channel UniFET

MOSFET

500 V, 15 A, 380 mΩ

Features

• Low gate charge Q

results in simple drive requirement

(Typ. 33 nC)

• Improved Gate, avalanche and high reapplied dv/dt

ruggedness

• Reduced R

DS(on)

( 330mΩ ( Typ.) @ V

= 10 V, I

= 7.5 A)

• Reduced Miller capacitance and low Input capacitance

(Typ. C

rss

= 16 pF)

• Improved switching speed with low EMI

• 175

C rated junction temperature

Applications

• Lighting

• Uninterruptible Power Supply

• AC-DC Power Supply

Description

UniFET

MOSFET is Fairchild Semiconductor’s high

voltage MOSFET family based on planar stripe and

DMOS technology. This MOSFET is tailored to reduce

on-state resistance, and to provide better switching

performance and higher avalanche energy strength. This

device family is suitable for switching power converter

applications such as power factor correction (PFC), flat

panel display (FPD) TV power, ATX and electronic lamp

ballasts.

-PAK

Absolute Maximum Ratings T

= 25

C unless otherwise noted.

Thermal Characteristics

Symbol Parameter

FDB15N50 Unit

DSS

Drain to Source Voltage 500 V

Gate to Source Voltage ±30 V

Drain Current

15 A

11 A

Continuous (T

= 25

C, V

= 10V)

Continuous (T

= 100

C, V

= 10V)

Pulsed (Note 1)

60 A

Power dissipation

Derate above 25

300

, T

STG

Operating and Storage Temperature -55 to 175

Soldering Temperature for 10 seconds 300 (1.6mm from case)

θJC

Thermal Resistance Junction to Case, Max.

0.50

C/W

θJA

Thermal Resistance Junction to Ambient, Max. 62

C/W

Symbol Parameter

FDB15N50 Unit

Summary of content (7 pages)

PAGE 1
FDB15N50 N-Channel UniFETTM MOSFET 500 V, 15 A, 380 mΩ Description Features UniFETTM MOSFET is Fairchild Semiconductor’s high voltage MOSFET family based on planar stripe and DMOS technology. This MOSFET is tailored to reduce on-state resistance, and to provide better switching performance and higher avalanche energy strength.
PAGE 2
Device Marking FDB15N50 Device FDB15N50 Package D2-PAK Reel Size 330 mm Tape Width 24 mm Quantity 800 units Electrical Characteristics TJ = 25°C unless otherwise noted. Symbol Parameter Test Conditions Min Typ Max 500 - - V - 0.58 - V/°C Unit Statics BVDSS Drain to Source Breakdown Voltage ∆BVDSS/∆TJ Breakdown Voltage Temp. Coefficient ID = 250µA, VGS = 0V Reference to 25oC, ID = 1mA RDS(ON) Drain to Source On-Resistance VGS = 10V, ID = 7.
PAGE 3
100 TJ = 25oC VGS DESCENDING ID, DRAIN TO SOURCE CURRENT (A) ID, DRAIN TO SOURCE CURRENT (A) 100 10V 6.5V 6V 5.5V 5V 4.5V 10 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 1 1 10 10 TJ = 175oC VGS DESCENDING 10V 6V 5.5V 5V 4.5V 4V PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 1 1 100 10 VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 1. Output Characteristics Figure 2. Output Characteristics 3.5 60 PULSE DURATION = 80µs DUTY CYCLE = 0.
PAGE 4
100 TC = 25oC 25 100µs ID, DRAIN CURRENT (A) ISD , SOURCE TO DRAIN CURRENT (A) 30 20 15 TJ = 175oC TJ = 25oC 10 5 10 1ms 10ms 1.0 OPERATION IN THIS AREA 0 0.3 0.1 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1 10 VSD , SOURCE TO DRAIN VOLTAGE (V) 1000 Figure 8. Maximum Safe Operating Area 16 IAS, AVALANCHE CURRENT (A) 50 12 8 4 0 25 50 75 100 125 150 If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R ≠ 0 tAV = (L/R)ln[(IAS*R)/(1.
PAGE 5
VDS BVDSS tP VDS L IAS VDD VARY tP TO OBTAIN REQUIRED PEAK IAS + RG VDD - VGS DUT tP IAS 0V 0 0.01Ω tAV Figure 12. Unclamped Energy Test Circuit Figure 13. Unclamped Energy Waveforms VDS VDD Qg(TOT) RL VGS = 10V VDS VGS + VDD VGS - VGS = 1V DUT 0 Ig(REF) Qg(TH) Qgs Qgd Ig(REF) 0 Figure 14. Gate Charge Test Circuit Figure 15. Gate Charge Waveforms VDS tON tOFF td(ON) td(OFF) tr RL VDS tf 90% 90% + VGS VDD 10% 10% 0 DUT 90% RGS VGS VGS 0 Figure 16.
PAGE 6
FDB15N50 — N-Channel UniFETTM MOSFET Mechanical Dimensions Figure 18. TO263 (D2PAK), Molded, 2-Lead, Surface Mount Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
PAGE 7
tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.