FDP3652 / FDB3652 N-Channel PowerTrench® MOSFET 100 V, 61 A, 16 mΩ Features Applications • rDS(on) = 14 mΩ ( Typ.), VGS = 10 V, ID = 61 A • Synchronous Rectification for ATX / Server / Telecom PSU • Qg(tot) = 41 nC ( Typ.
Device Marking Device Package Reel Size Tape Width Quantity FDB3652 FDB3652 D2-PAK 330 mm 24 mm 800 units FDP3652 FDP3652 TO-220 Tube N/A 50 units Electrical Characteristics TC = 25°C unless otherwise noted Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics B VDSS Drain to Source Breakdown Voltage IDSS Zero Gate Voltage Drain Current IGSS Gate to Source Leakage Current ID = 250µA, VGS = 0V 100 - - V - - 1 - - 250 µA VGS = ±20V - - ±100 nA V
1.2 75 ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER 1.0 0.8 0.6 0.4 50 25 0.2 0 0 0 25 50 75 100 150 125 175 25 50 75 TC , CASE TEMPERATURE (o C) 100 125 150 175 TC, CASE TEMPERATURE (oC) Figure 1. Normalized Power Dissipation vs Ambient Temperature Figure 2. Maximum Continuous Drain Current vs Case Temperature 2 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 ZθJC, NORMALIZED THERMAL IMPEDANCE 1 PDM 0.
1000 500 If R = 0 tAV = (L)(I AS)/(1.3*RATED BVDSS - VDD) If R ¼ 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] IAS, AVALANCHE CURRENT (A) ID, DRAIN CURRENT (A) 10µs 100 100µs 10 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 1ms 1 10ms SINGLE PULSE TJ = MAX RATED TC = 25oC 100 STARTING TJ = 25oC 10 STARTING TJ = 150oC DC 0.1 1 1 10 100 VDS, DRAIN TO SOURCE VOLTAGE (V) 200 10 NOTE: Refer to Fairchild Application Notes AN7514 and AN7515 Figure 5.
1.4 1.2 VGS = VDS, ID = 250µA NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE ID = 250µA NORMALIZED GATE THRESHOLD VOLTAGE 1.2 1.0 0.8 0.6 0.4 -80 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC) 200 -80 0 40 80 120 160 TJ , JUNCTION TEMPERATURE (oC) 200 10 VGS , GATE TO SOURCE VOLTAGE (V) CISS = CGS + CGD C, CAPACITANCE (pF) -40 Figure 12.
VDS BVDSS tP L VDS VARY tP TO OBTAIN REQUIRED PEAK IAS IAS + RG VDD VDD - VGS DUT tP IAS 0V 0 0.01Ω tAV Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms VDS VDD Qg(TOT) VDS L VGS VGS VGS = 10V + Qgs2 VDD DUT VGS = 2V Ig(REF) 0 Qg(TH) Qgs Qgd Ig(REF) 0 Figure 18. Gate Charge Waveforms Figure 17. Gate Charge Test Circuit VDS tON tOFF td(ON) td(OFF) RL tr VDS tf 90% 90% + VGS VDD - 10% 0 10% DUT 90% RGS VGS VGS 0 Figure 19.
The maximum rated junction temperature, TJM , and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM , in an application. Therefore the application’s ambient temperature, TA (oC), and thermal resistance RθJA (oC/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part. RθJA = 26.51+ 19.84/(0.262+Area) EQ.2 RθJA = 26.
.SUBCKT FDP3652 2 1 3 rev March 2002 Ca 12 8 1.1e-9 Cb 15 14 1.1e-9 Cin 6 8 2.8e-9 LDRAIN DPLCAP 10 Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD Dplcap 10 5 DplcapMOD RLDRAIN RSLC1 51 5 51 EVTHRES + 19 8 + LGATE GATE 1 ESLC 11 + 17 EBREAK 18 - 50 RDRAIN 6 8 ESG DBREAK + RSLC2 Ebreak 11 7 17 18 108.2 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1 It 8 17 1 DRAIN 2 5 EVTEMP RGATE + 18 22 9 20 21 16 DBODY MWEAK 6 MMED MSTRO RLGATE Lgate 1 9 7.
REV March 2002 template FDP3652 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl=1.5e-11,nl=1.06,rs=2.5e-3,trs1=2.4e-3,trs2=1.1e-6,cjo=1.9e-9,m=5.8e-1,tt=2.5e-8,xti=3.9) dp..model dbreakmod = (rs=2.7e-1,trs1=1e-3,trs2=-8.9e-6) dp..model dplcapmod = (cjo=7e-10,isl=10e-30,nl=10,m=0.58) m..model mmedmod = (type=_n,vto=3.6,kp=5.5,is=1e-30, tox=1) m..model mstrongmod = (type=_n,vto=4.3,kp=110,is=1e-30, tox=1) m..model mweakmod = (type=_n,vto=3,kp=0.03,is=1e-30, tox=1,rs=.1) sw_vcsp..
th JUNCTION REV 23 March 2002 FDP3652 CTHERM1 TH 6 1e-2 CTHERM2 6 5 1.5e-2 CTHERM3 5 4 2e-2 CTHERM4 4 3 2.1e-2 CTHERM5 3 2 2.2e-2 CTHERM6 2 TL 9e-2 RTHERM1 CTHERM1 6 RTHERM1 TH 6 2.7e-2 RTHERM2 6 5 2.8e-2 RTHERM3 5 4 7.8e-2 RTHERM4 4 3 9e-2 RTHERM5 3 2 2.7e-1 RTHERM6 2 TL 2.87e-1 RTHERM2 CTHERM2 5 SABER Thermal Model RTHERM3 SABER thermal model FDP3652 template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 =1e-2 ctherm.ctherm2 6 5 =1.5e-2 ctherm.ctherm3 5 4 =2e-2 ctherm.
FDP3652 / FDB3652 — N-Channel PowerTrench® MOSFET Mechanical Dimensions TO-220 3L Figure 22. TO-220, Molded, 3Lead, Jedec Variation AB Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
FDP3652 / FDB3652 — N-Channel PowerTrench® MOSFET Mechanical Dimensions TO-263 2L (D2PAK) Figure 23. 2LD, TO263, Surface Mount Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.