Datasheet

August 1997
FDC6303N
Digital FET, Dual N-Channel
General Description Features
Absolute Maximum Ratings T
A
= 25°C unless otherwise noted
Symbol Parameter FDC6303N Units
V
DSS
Drain-Source Voltage 25 V
V
GSS
Gate-Source Voltage 8 V
I
D
Drain Current - Continuous 0.68 A
- Pulsed 2
P
D
Maximum Power Dissipation (Note 1a) 0.9 W
(Note 1b) 0.7
T
J
,T
STG
Operating and Storage Temperature Range -55 to 150 °C
ESD Electrostatic Discharge Rating MIL-STD-883D
Human Body Model (100pf / 1500 Ohm)
6.0 kV
THERMAL CHARACTERISTICS
R
θ
JA
Thermal Resistance, Junction-to-Ambient (Note 1a) 140 °C/W
R
θ
JC
Thermal Resistance, Junction-to-Case (Note 1) 60 °C/W
FDC6303N Rev.C
25 V, 0.68 A continuous, 2 A Peak.
R
DS(ON)
= 0.6 Ω @ V
GS
= 2.7 V
R
DS(ON)
= 0.45 Ω @ V
GS
= 4.5 V.
Very low level gate drive requirements allowing direct
operation in 3V circuits. V
GS(th)
< 1.5 V.
Gate-Source Zener for ESD ruggedness.
>6kV Human Body Model
Replace multiple NPN digital transistors (IMHxA series)
with one DMOS FET.
These dual N-Channel logic level enhancement mode field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state
resistance. This device has been designed especially for
low voltage applications as a replacement for digital
transistors in load switching applications. Since bias
resistors are not required this one N-Channel FET can
replace several digital transistors with different bias
resistors like the IMHxA series.
1
5
3
2
4
6
SOT-23
SuperSOT
TM
-8
SOIC-16
SO-8
SOT-223
SuperSOT
TM
-6
Mark: .303
© 1997 Fairchild Semiconductor Corporation