Datasheet

July 1997
FDC6304P
Digital FET, Dual P-Channel
General Description Features
Absolute Maximum Ratings T
A
= 25
o
C unless other wise noted
Symbol Parameter FDC6304P Units
V
DSS
Drain-Source Voltage -25 V
V
GSS
Gate-Source Voltage -8 V
I
D
Drain Current - Continuous -0.46 A
- Pulsed -1
P
D
Maximum Power Dissipation (Note 1a) 0.9 W
(Note 1b) 0.7
T
J
,T
STG
Operating and Storage Temperature Range -55 to 150 °C
ESD Electrostatic Discharge Rating MIL-STD-883D
Human Body Model (100pf / 1500 Ohm)
6.0 kV
THERMAL CHARACTERISTICS
R
θ
JA
Thermal Resistance, Junction-to-Ambient (Note 1a) 140 °C/W
R
θ
JC
Thermal Resistance, Junction-to-Case (Note 1) 60 °C/W
FDC6304P Rev.D
-25 V, -0.46 A continuous, -1.0 A Peak.
R
DS(ON)
= 1.5 @ V
GS
= -2.7 V
R
DS(ON)
= 1.1 @ V
GS
= -4.5 V.
Very low level gate drive requirements allowing direct
operation in 3V circuits. V
GS(th)
< 1.5 V.
Gate-Source Zener for ESD ruggedness.
>6kV Human Body Model.
These P-Channel enhancement mode field effect transistor are
produced using Fairchild's proprietary, high cell density, DMOS
technology. This very high density process is tailored to minimize
on-state resistance at low gate drive conditions. This device is
designed especially for application in battery power applications
such as notebook computers and cellular phones. This device
has excellent on-state resistance even at gate drive voltages as
low as 2.5 volts.
Mark: .304
SOT-23
SuperSOT
TM
-8
SOIC-16
SO-8
SOT-223
SuperSOT
TM
-6
5
6
3
2
1
4
© 1997 Fairchild Semiconductor Corporation

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