Datasheet

April 1999
FDC6321C
Dual N & P Channel , Digital FET
General Description Features
Absolute Maximum Ratings T
A
= 25
o
C unless other wise noted
Symbol Parameter N-Channel P-Channel Units
V
DSS
, V
CC
Drain-Source Voltage, Power Supply Voltage 25 -25 V
V
GSS
, V
IN
Gate-Source Voltage, 8 -8 V
I
D
, I
O
Drain/Output Current - Continuous 0.68 -0.46 A
- Pulsed 2 -1.5
P
D
Maximum Power Dissipation (Note 1a)
(Note 1b)
0.9 W
0.7
T
J
,T
STG
Operating and Storage Tempature Ranger -55 to 150 °C
ESD Electrostatic Discharge Rating MIL-STD-883D
Human Body Model (100pf / 1500 Ohm)
6 kV
THERMAL CHARACTERISTICS
R
θ
JA
Thermal Resistance, Junction-to-Ambient (Note 1a) 140 °C/W
R
θ
JC
Thermal Resistance, Junction-to-Case (Note 1) 60 °C/W
FDC6321C.RevB
N-Ch 25 V, 0.68 A, R
DS(ON)
= 0.45 Ω @ V
GS
= 4.5 V
P-Ch -25 V, -0.46 A, R
DS(ON)
= 1.1 Ω @ V
GS
= -4.5 V.
Very low level gate drive requirements allowing direct
operation in 3 V circuits. V
GS(th)
< 1.0V.
Gate-Source Zener for ESD ruggedness.
>6kV Human Body Model
Replace multiple dual NPN & PNP digital transistors.
These dual N & P Channel logic level enhancement mode
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very
high density process is especially tailored to minimize
on-state resistance. This device has been designed
especially for low voltage applications as a replacement for
digital transistors in load switching applications. Since bias
resistors are not required this dual digital FET can replace
several digital transistors with different bias resistors.
SOT-23
SuperSOT
TM
-8
SOIC-16
SO-8
SOT-223
SuperSOT
TM
-6
Mark:.321
1
5
3
2
6
4
D1
S2
G1
D2
S1
G2
SuperSOT -6
TM
© 1999 Fairchild Semiconductor Corporation