Datasheet
November 1997
FDC653N
N-Channel Enhancement Mode Field Effect Transistor
General Description Features
Absolute Maximum Ratings T
A
= 25°C unless otherwise note
Symbol Parameter FDC653N Units
V
DSS
Drain-Source Voltage 30 V
V
GSS
Gate-Source Voltage - Continuous ±20 V
I
D
Drain Current - Continuous (Note 1a) 5 A
- Pulsed 15
P
D
Maximum Power Dissipation (Note 1a) 1.6 W
(Note 1b)
0.8
T
J
,T
STG
Operating and Storage Temperature Range -55 to 150 °C
THERMAL CHARACTERISTICS
R
θJA
Thermal Resistance, Junction-to-Ambient (Note 1a) 78 °C/W
R
θJC
Thermal Resistance, Junction-to-Case (Note 1) 30 °C/W
FDC653N Rev.C
This N-Channel enhancement mode power field effect
transistors is produced using Fairchild's proprietary, high cell
density, DMOS technology. This very high density process is
tailored to minimize on-state resistance. These devices are
particularly suited for low voltage applications in notebook
computers, portable phones, PCMICA cards, and other
battery powered circuits where fast switching, and low in-line
power loss are needed in a very small outline surface mount
package.
5 A, 30 V. R
DS(ON)
= 0.035 Ω @ V
GS
= 10 V
R
DS(ON)
= 0.055 Ω @ V
GS
= 4.5 V.
Proprietary SuperSOT
TM
-6 package design using copper
lead frame for superior thermal and electrical capabilities.
High density cell design for extremely low R
DS(ON)
.
Exceptional on-resistance and maximum DC current
capability.
SOIC-16
SOT-23
SuperSOT
TM
-8
SO-8
SOT-223
SuperSOT
TM
-6
3
5
6
4
1
2
3
D
D
D
S
D
G
SuperSOT -6
TM
.653
pin
1
© 1997 Fairchild Semiconductor Corporation