Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFDC8602, MOSFET

May 2013

FDC8602 Dual N-Channel Shielded Gate PowerTrench

MOSFET

FDC8602 Rev.C1

FDC8602

Dual N-Channel Shielded Gate PowerTrench

MOSFET

100 V, 1.2 A, 350 mΩ

Features

 Shielded Gate MOSFET Technology

 Max r

DS(on)

= 350 mΩ at V

= 10 V, I

= 1.2 A

 Max r

DS(on)

= 575 mΩ at V

= 6 V, I

= 0.9 A

 High performance trench technology for extremely low r

DS(on)

 High power and current handling capability in a widely used

surface mount package

 Fast switching speed

 100% UIL Tested

 RoHS Compliant

General Description

This N-Channel MOSFET is produced using Fairchild

Semiconductor‘s advanced PowerTrench

process that

incorporates Shielded Gate technology. This process has been

optimized

for r

DS(on)

, switching performance and ruggedness.

Applications

 Load Switch

 Synchronous Rectifier

SuperSOT

-6

Pin 1

MOSFET Maximum Ratings T

= 25 °C unless otherwise noted

Thermal Characteristics

Package Marking and Ordering Information

Symbol Parameter Ratings Units

Drain to Source Voltage 100 V

Gate to Source Voltage ±20 V

Drain Current -Continuous (Note 1a) 1.2 A

-Pulsed 5 A

Single Pulse Avalanche Energy (Note 3) 1.5 mJ

Power Dissipation (Note 1a) 0.96

Power Dissipation (Note 1b) 0.69

, T

STG

Operating and Storage Junction Temperature Range -55 to +150 °C

θJC

Thermal Resistance, Junction to Case 60

°C/W

θJA

Thermal Resistance, Junction to Ambient (Note 1a) 130

Device Marking Device Package Reel Size Tape Width Quantity

.862 FDC8602 SSOT-6 7 ’’ 8

mm 3000 units

Summary of content (7 pages)

PAGE 1
FDC8602 Dual N-Channel Shielded Gate PowerTrench® MOSFET 100 V, 1.2 A, 350 mΩ Features General Description Shielded Gate MOSFET Technology This Max rDS(on) = 350 mΩ at VGS = 10 V, ID = 1.2 A Semiconductor‘s Max rDS(on) = 575 mΩ at VGS = 6 V, ID = 0.9 A incorporates Shielded Gate technology. This process has been N-Channel MOSFET is advanced PowerTrench® produced using Fairchild process that optimized for rDS(on), switching performance and ruggedness.
PAGE 2
Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V ΔBVDSS ΔTJ Breakdown Voltage Temperature Coefficient ID = 250 μA, referenced to 25 °C IDSS Zero Gate Voltage Drain Current VDS = 80 V, VGS = 0 V 1 μA IGSS Gate to Source Leakage Current VGS = ±20 V, VDS = 0 V ±100 nA 4 V 100 V 73 mV/°C On Characteristics VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250 μA ΔVGS(th) ΔTJ Gate to Source
PAGE 3
5 4 ID, DRAIN CURRENT (A) NORMALIZED DRAIN TO SOURCE ON-RESISTANCE VGS = 8 V VGS = 10 V VGS = 7 V 4 3 VGS = 6 V 2 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 1 VGS = 5 V 0 0 1 2 3 4 VGS = 5 V VGS = 6 V 3 VGS = 7 V 2 VGS = 8 V 1 0 5 0 1 2 Figure 1. On Region Characteristics 4 5 Figure 2. Normalized On-Resistance vs Drain Current and Gate Voltage 2.0 1200 ID = 1.2 A 1.8 VGS = 10 V rDS(on), DRAIN TO 1.6 1.4 1.2 1.0 0.8 0.
PAGE 4
VGS, GATE TO SOURCE VOLTAGE (V) 10 500 VDD = 50 V ID = 1.2 A Ciss CAPACITANCE (pF) 8 VDD = 75 V VDD = 25 V 6 4 10 1 2 0 0.2 0.4 0.6 0.8 1.0 1.2 0.1 0.1 1.4 1 10 100 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) Figure 7. Gate Charge Characteristics Figure 8. Capacitance vs Drain to Source Voltage 10 ID, DRAIN CURRENT (A) 2 IAS, AVALANCHE CURRENT (A) Crss f = 1 MHz VGS = 0 V 0 1 TJ = 25 oC TJ = 100 oC 1 0.1 0.1 1 0.005 0.
PAGE 5
2 DUTY CYCLE-DESCENDING ORDER NORMALIZED THERMAL IMPEDANCE, ZθJA 1 0.1 D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 SINGLE PULSE NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA o RθJA = 180 C/W 0.01 0.005 -4 10 -3 10 -2 10 -1 10 1 10 100 1000 t, RECTANGULAR PULSE DURATION (sec) Figure 12. Junction-to-Ambient Transient Thermal Response Curve ©2011 Fairchild Semiconductor Corporation FDC8602 Rev.C1 5 www.fairchildsemi.
PAGE 6
FDC8602 Dual N-Channel Shielded Gate PowerTrench® MOSFET Dimensional Outline and Pad Layout ©2011 Fairchild Semiconductor Corporation FDC8602 Rev.C1 6 www.fairchildsemi.
PAGE 7
tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.