Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFDD10AN06A0, MOSFET

January 2014

FDD10AN06A0 — N-Channel PowerTrench

MOSFET

www.fairchildsemi.com

FDD10AN06A0

Features

Applications

N-Channel PowerTrench

MOSFET

60 V, 50 A, 10.5 mΩ

•

DS(on)

= 9.4 mΩ (Typ.) @ V

= 10 V, I

= 50 A

G(tot)

= 28 nC (Typ.) @ V

= 10 V

Low Miller Charge

Low Q

Body Diode

UIS Capability (Single Pulse and Repetitive Pulse)

• LED TV

• Synchronous Rectification

• Consumer Appliances

D-PAK

MOSFET Maximum Ratings T

= 25°C unless otherwise noted

Symbol Parameter

FDD10AN06A0

Unit

DSS

Drain to Source Voltage 60 V

Gate to Source Voltage ±20 V

50 A

Drain Current

Continuous (T

< 115

C, V

= 10V)

Continuous (T

amb

= 25

C, V

= 10V, with R

θJA

= 52

C/W) 11 A

Pulsed Figure 4 A

Single Pulse Avalanche Energy (Note 1) 429 mJ

Power dissipation 135 W

Derate above 25

C0.9

CW/

, T

STG

Operating and Storage Temperature -55 to 175

Thermal Resistance, Junction to Ambient, 1in copper pad area, Max.

Thermal Resistance, Junction to Ambient, Max. 100

Thermal Resistance, Junction to Case, Max.

1.11

Thermal Characteristics

θJC

C/W

θJA

C/W

θJA

2 o

C/W

Description

This N-Channel MOSFET has been designed specifically

to improve the overall efficiency of DC/DC converters

using either synchronous or conventional switching PWM

controllers. These MOSFETs feature faster switching and

lower gate charge than other MOSFETs with comparable

RDS(ON) specifications. The result is a MOSFET that is

easy and safer to

drive (even at very high frequencies),

and DC/DC power supply designs with higher reliability

and system efficiency.

FDD10AN06A0

Rev. C3

Summary of content (12 pages)

PAGE 1
FDD10AN06A0 N-Channel PowerTrench® MOSFET 60 V, 50 A, 10.5 mΩ Features Description • RDS(on) = 9.4 mΩ (Typ.) @ VGS = 10 V, ID = 50 A This N-Channel MOSFET has been designed specifically to improve the overall efficiency of DC/DC converters using either synchronous or conventional switching PWM controllers. These MOSFETs feature faster switching and lower gate charge than other MOSFETs with comparable RDS(ON) specifications.
PAGE 2
Device Marking FDD10AN06A0 Device FDD10AN06A0 Package D-PAK Reel Size 330 mm Tape Width 16 mm Quantity 2500 units Electrical Characteristics TC = 25°C unless otherwise noted Symbol Parameter Test Conditions Min Typ Max Unit V Off Characteristics B VDSS Drain to Source Breakdown Voltage IDSS Zero Gate Voltage Drain Current IGSS Gate to Source Leakage Current ID = 250µA, VGS = 0V 60 - - - - 1 - - 250 VGS = ±20V - - ±100 nA VGS = VDS, ID = 250µA 2 - 4 V ID = 25A, VGS = 6
PAGE 3
1.2 80 CURRENT LIMITED BY PACKAGE ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER 1.0 0.8 0.6 0.4 0.2 0 0 25 50 75 100 150 125 60 40 20 0 175 25 50 75 TC , CASE TEMPERATURE (oC) Figure 1. Normalized Power Dissipation vs Ambient Temperature 2 ZθJC, NORMALIZED THERMAL IMPEDANCE 1 100 125 150 175 TC, CASE TEMPERATURE (oC) Figure 2. Maximum Continuous Drain Current vs Case Temperature DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM 0.
PAGE 4
500 500 If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R ≠ 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] ID, DRAIN CURRENT (A) 100 IAS, AVALANCHE CURRENT (A) 10µs 100µs 1ms OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 10 10ms DC 1 SINGLE PULSE TJ = MAX RATED TC = 25oC 0.1 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 10 STARTING TJ = 150oC 1 0.01 100 TJ = 25oC 25 75 VGS = 6V 50 TJ = -55oC TC = 25oC 4 5 VGS , GATE TO SOURCE VOLTAGE (V) 0 7 0.5 1.0 1.5 2.0 Figure 8.
PAGE 5
1.4 1.2 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE VGS = VDS, ID = 250µA NORMALIZED GATE THRESHOLD VOLTAGE 1.2 1.0 0.8 0.6 0.4 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE ( C) Figure 11. Normalized Gate Threshold Voltage vs Junction Temperature VGS , GATE TO SOURCE VOLTAGE (V) 10 C, CAPACITANCE (pF) CISS = CGS + CGD COSS ≅ CDS + CGD CRSS = CGD 100 VGS = 0V, f = 1MHz 0.1 1.
PAGE 6
VDS BVDSS tP L VARY tP TO OBTAIN REQUIRED PEAK IAS + RG - VGS VDS IAS VDD VDD DUT tP 0V IAS 0 0.01Ω tAV Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms VDS VDD Qg(TOT) VDS L VGS + - VGS VGS = 10V Qgs2 VDD DUT VGS = 2V Ig(REF) 0 Qg(TH) Qgs Qgd Ig(REF) 0 Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms VDS tON tOFF td(ON) td(OFF) RL tr VDS 90% - VDD 10% 0 10% DUT 90% VGS VGS 0 Figure 19.
PAGE 7
The maximum rated junction temperature, TJM , and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM , in an application. Therefore the application’s ambient temperature, TA (oC), and thermal resistance RθJA (oC/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part. RθJA = 33.32+ 23.84/(0.268+Area) EQ.2 RθJA = 33.
PAGE 8
.SUBCKT FDD10AN06A0 2 1 3 ; Ca 12 8 7e-10 Cb 15 14 7e-10 Cin 6 8 1.8e-9 rev July 2002 DPLCAP 10 RSLC2 + GATE 1 Lgate 1 9 3.2e-9 Ldrain 2 5 1.0e-9 Lsource 3 7 1.2e-9 RLGATE EVTEMP RGATE + 18 22 9 20 ESLC 11 50 EVTHRES + 19 8 6 21 EBREAK 16 + 17 18 - DBODY MWEAK MMED MSTRO CIN LSOURCE 8 7 RSOURCE RLgate 1 9 32 RLdrain 2 5 10 RLsource 3 7 12 Mmed 16 6 8 8 MmedMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD DBREAK RDRAIN 6 8 ESG LGATE 5 51 - Ebreak 11 7 17 18 67.
PAGE 9
REV July 2002 template FDD10AN06A0 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl=2e-11,nl=1.06,rs=3.3e-3,trs1=2.4e-3,trs2=1.1e-6,cjo=1.25e-9,m=5.3e-1,tt=4.2e-8,xti=3.9) dp..model dbreakmod = (rs=2.7e-1,trs1=1e-3,trs2=-8.9e-6) dp..model dplcapmod = (cjo=4.7e-10,isl=10e-30,nl=10,m=0.44) m..model mmedmod = (type=_n,vto=3.5,kp=5.5,is=1e-30, tox=1) m..model mstrongmod = (type=_n,vto=4.25,kp=80,is=1e-30, tox=1) m..model mweakmod = (type=_n,vto=2.92,kp=0.03,is=1e-30, tox=1,rs=0.
PAGE 10
th JUNCTION REV 23 July 2002 FDD10AN06A0T CTHERM1 TH 6 3.2e-3 CTHERM2 6 5 3.3e-3 CTHERM3 5 4 3.4e-3 CTHERM4 4 3 3.5e-3 CTHERM5 3 2 6.4e-3 CTHERM6 2 TL 1.9e-2 RTHERM1 CTHERM1 6 RTHERM1 TH 6 5.5e-4 RTHERM2 6 5 5.0e-3 RTHERM3 5 4 4.5e-2 RTHERM4 4 3 1.5e-1 RTHERM5 3 2 3.37e-1 RTHERM6 2 TL 3.5e-1 RTHERM2 CTHERM2 5 SABER Thermal Model RTHERM3 SABER thermal model FDD10AN06A0T template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 =3.2e-3 ctherm.ctherm2 6 5 =3.3e-3 ctherm.ctherm3 5 4 =3.
PAGE 11
FDD10AN06A0 — N-Channel PowerTrench® MOSFET Mechanical Dimensions Figure 22. TO252 (D-PAK), Molded, 3-Lead, Option AA&AB Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
PAGE 12
tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.