FDD120AN15A0 N-Channel PowerTrench® MOSFET 150 V, 14 A, 120 mΩ Features Applications • RDS(on) = 101 mΩ ( Typ.) @ VGS = 10 V, ID = 4 A • Consumer Appliances • QG(tot) = 11.2 nC ( Typ.
Device Marking FDD120AN15A0 Device FDD120AN15A0 Package D-PAK Reel Size 330 mm Tape Width 16 mm Quantity 2500 units Electrical Characteristics TC = 25°C unless otherwise noted Symbol Parameter Test Conditions Min Typ Max Unit Off Characteristics B VDSS Drain to Source Breakdown Voltage IDSS Zero Gate Voltage Drain Current IGSS Gate to Source Leakage Current ID = 250µA, VGS = 0V 150 - - V - - 1 - - 250 µA VGS = ±20V - - ±100 nA V V DS = 120V VGS = 0V TC = 150oC On Chara
1.2 15 12 ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER 1.0 0.8 0.6 0.4 9 6 3 0.2 0 0 25 50 75 100 150 125 0 175 25 50 75 TC , CASE TEMPERATURE (oC) Figure 1. Normalized Power Dissipation vs Ambient Temperature 2 ZθJC, NORMALIZED THERMAL IMPEDANCE 1 100 125 150 175 TC, CASE TEMPERATURE (oC) Figure 2. Maximum Continuous Drain Current vs Case Temperature DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM 0.
50 10µs IAS, AVALANCHE CURRENT (A) ID, DRAIN CURRENT (A) 100 100µs 10 1ms OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 1 0.1 SINGLE PULSE TJ = MAX RATED TC = 25o C 1 10ms DC 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 100 Figure 6. Unclamped Inductive Switching Capability 30 ID, DRAIN CURRENT (A) TJ = 25oC TJ = 175 oC 15 10 5 TJ = -55o C VGS = 5V 0 4 5 VGS , GATE TO SOURCE VOLTAGE (V) 2.
1.2 VGS = VDS, ID = 250µA NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE NORMALIZED GATE THRESHOLD VOLTAGE 1.2 1.0 0.8 0.6 0.4 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC) 1.1 1.0 0.9 -80 200 Figure 11. Normalized Gate Threshold Voltage vs Junction Temperature 10 VGS , GATE TO SOURCE VOLTAGE (V) C ISS = CGS + C GD COSS ≅ CDS + CGD 100 CRSS = CGD 10 VGS = 0V, f = 1MHz 5 0.
VDS BVDSS tP L VARY tP TO OBTAIN REQUIRED PEAK IAS + RG - VGS VDS IAS VDD VDD DUT tP 0V IAS 0 0.01Ω tAV Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms VDS VDD Qg(TOT) VDS L VGS + - VGS VGS = 10V Qgs2 VDD DUT VGS = 2V Ig(REF) 0 Qg(TH) Qgs Qgd Ig(REF) 0 Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms VDS tON tOFF td(ON) td(OFF) RL tr VDS 90% - VDD 10% 0 10% DUT 90% VGS VGS 0 Figure 19.
The maximum rated junction temperature, TJM , and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM , in an application. Therefore the application’s ambient temperature, TA (oC), and thermal resistance RθJA (oC/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part. RθJA = 33.32+ 23.84/(0.268+Area) EQ.2 RθJA = 33.
.SUBCKT FDD120AN15A0 2 1 3 ; Ca 12 8 2.5e-10 Cb 15 14 2.5e-10 Cin 6 8 7.5e-10 rev July 2002 DPLCAP 10 RSLC2 + GATE 1 Lgate 1 9 3e-9 Ldrain 2 5 1.
REV July 2002 template FDD120AN15A0 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl=4e-12,nl=1.07,rs=6.5e-3,trs1=3.0e-3,trs2=1.5e-6,cjo=5.5e-10,m=0.65,tt=5e-8,xti=4.2) dp..model dbreakmod = (rs=0.5,trs1=1e-3,trs2=-1e-6) dp..model dplcapmod = (cjo=1.56e-10,isl=10.0e-30,nl=10,m=0.62) m..model mmedmod = (type=_n,vto=3.6,kp=1.8,is=1e-30, tox=1) m..model mstrongmod = (type=_n,vto=4.4,kp=30,is=1e-30, tox=1) m..model mweakmod = (type=_n,vto=3.14,kp=0.02,is=1e-30, tox=1,rs=0.1) LDRAIN sw_vcsp..
th JUNCTION REV 23 July 2002 FDD120AN15A0T CTHERM1 TH 6 1.2e-3 CTHERM2 6 5 2e-3 CTHERM3 5 4 2.5e-3 CTHERM4 4 3 3.15e-3 CTHERM5 3 2 3.3e-3 CTHERM6 2 TL 1.35e-2 RTHERM1 CTHERM1 6 RTHERM1 TH 6 6.8e-2 RTHERM2 6 5 1.18e-1 RTHERM3 5 4 2.28e-1 RTHERM4 4 3 3.28e-1 RTHERM5 3 2 5.28e-1 RTHERM6 2 TL 5.78e-1 RTHERM2 CTHERM2 5 SABER Thermal Model RTHERM3 SABER thermal model FDD120AN15A0T template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 =1.2e-3 ctherm.ctherm2 6 5 =2e-3 ctherm.ctherm3 5 4 =2.
FDD120AN15A0 — N-Channel PowerTrench® MOSFET Mechanical Dimensions TO-252 3L (DPAK) Figure 21. TO252 (D-PAK), Molded, 3 Lead, Option AA&AB Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
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