FDD13AN06A0 N-Channel PowerTrench® MOSFET 60 V, 50 A, 13 mΩ Features Applications • RDS(on) = 11.5 mΩ ( Typ.) @ VGS = 10 V, ID = 50 A • Consumer Appliances • QG(tot) = 22 nC ( Typ.
Device Marking FDD13AN06A0 Device FDD13AN06A0 Package D-PAK Reel Size 330 mm Tape Width 16 mm Quantity 2500 units Electrical Characteristics TC = 25°C unless otherwise noted Symbol Parameter Test Conditions Min Typ Max Unit V Off Characteristics B VDSS Drain to Source Breakdown Voltage IDSS Zero Gate Voltage Drain Current IGSS Gate to Source Leakage Current ID = 250µA, VGS = 0V 60 - - - - 1 - - 250 VGS = ±20V - - ±100 nA VGS = VDS, ID = 250µA 2 - 4 V ID = 25A, VGS = 6
1.2 80 ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER 1.0 0.8 0.6 0.4 CURRENT LIMITED BY PACKAGE 60 40 20 0.2 0 0 0 25 50 75 100 150 125 175 25 50 75 TC , CASE TEMPERATURE (o C) ZθJC, NORMALIZED THERMAL IMPEDANCE 1 125 150 175 o TC, CASE TEMPERATURE ( C) Figure 1. Normalized Power Dissipation vs Ambient Temperature 2 100 Figure 2. Maximum Continuous Drain Current vs Case Temperature DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM 0.
100 1000 If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R ≠ 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] 100 100µs 1ms OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 10 1 0.1 IAS, AVALANCHE CURRENT (A) ID, DRAIN CURRENT (A) 10µs SINGLE PULSE TJ = MAX RATED TC = 25oC 1 DC 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 10ms 0.01 TJ = 175 oC TJ = -55oC TC = 25oC VGS = 20V 80 ID, DRAIN CURRENT (A) ID , DRAIN CURRENT (A) 100 Figure 6.
1.4 1.2 ID = 250µA NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE VGS = VDS, I D = 250µA NORMALIZED GATE THRESHOLD VOLTAGE 1.2 1.0 0.8 0.6 0.4 -80 -40 0 40 80 120 160 1.1 1.0 0.9 200 o -80 -40 TJ, JUNCTION TEMPERATURE ( C) Figure 11. Normalized Gate Threshold Voltage vs Junction Temperature VGS , GATE TO SOURCE VOLTAGE (V) C, CAPACITANCE (pF) 10 CISS = CGS + C GD COSS ≅ C DS + C GD CRSS = CGD 100 VGS = 0V, f = 1MHz 40 0.
VDS BVDSS tP L VARY tP TO OBTAIN REQUIRED PEAK IAS + RG - VGS VDS IAS VDD VDD DUT tP 0V IAS 0 0.01Ω tAV Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms VDS VDD Qg(TOT) VDS L VGS + - VGS VGS = 10V Qgs2 VDD DUT VGS = 2V Ig(REF) 0 Qg(TH) Qgs Qgd Ig(REF) 0 Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms VDS tON tOFF td(ON) td(OFF) RL tr VDS 90% - VDD 10% 0 10% DUT 90% VGS VGS 0 Figure 19.
The maximum rated junction temperature, TJM , and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM , in an application. Therefore the application’s ambient temperature, TA (oC), and thermal resistance RθJA (oC/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part. RθJA = 33.32+ 23.84/(0.268+Area) EQ.2 RθJA = 33.
.SUBCKT FDD13AN06A0 2 1 3 ; rev August 2002 Ca 12 8 5.1e-10 Cb 15 14 5.8e-10 Cin 6 8 1.3e-9 DPLCAP 10 RSLC2 + GATE 1 Lgate 1 9 5.2e-9 Ldrain 2 5 1.0e-9 Lsource 3 7 2.14e-9 RLGATE EVTEMP RGATE + 18 22 9 20 ESLC 11 50 EVTHRES + 19 8 6 21 EBREAK 16 + 17 18 - DBODY MWEAK MMED MSTRO CIN LSOURCE 8 7 RSOURCE RLgate 1 9 52 RLdrain 2 5 10 RLsource 3 7 21.4 Mmed 16 6 8 8 MmedMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD DBREAK RDRAIN 6 8 ESG LGATE 5 51 - Ebreak 11 7 17 18 65.
rev August 2002 template FDD13AN06A0 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl=1.0e-11,nl=1.08,rs=3.5e-3,trs1=2.2e-3,trs2=2.5e-9,cjo=.9e-9,m=5.1e-1,tt=1e-9,xti=3.9) dp..model dbreakmod = (rs=1.5e-1,trs1=1e-3,trs2=-8.9e-6) dp..model dplcapmod = (cjo=4.1e-10,isl=10e-30,nl=10,m=0.45) m..model mmedmod = (type=_n,vto=3.5,kp=6,is=1e-30, tox=1) m..model mstrongmod = (type=_n,vto=4.3,kp=50,is=1e-30, tox=1) m..model mweakmod = (type=_n,vto=2.91,kp=0.05,is=1e-30, tox=1,rs=0.
th REV 22 August 2002 JUNCTION FDD13AN06A0T CTHERM1 TH 6 9.7e-4 CTHERM2 6 5 6.2e-3 CTHERM3 5 4 4.6e-3 CTHERM4 4 3 4.9e-3 CTHERM5 3 2 8e-3 CTHERM6 2 TL 4.2e-2 RTHERM1 RTHERM1 TH 6 5.24e-2 RTHERM2 6 5 10.08e-2 RTHERM3 5 4 4.28e-1 RTHERM4 4 3 1.8e-1 RTHERM5 3 2 1.9e-1 RTHERM6 2 TL 2.1e-1 RTHERM2 CTHERM1 6 CTHERM2 5 SABER Thermal Model SABER thermal model FDD13AN06A0T template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 =9.7e-4 ctherm.ctherm2 6 5 =6.2e-3 ctherm.ctherm3 5 4 =4.
FDD13AN06A0 — N-Channel PowerTrench® MOSFET Mechanical Dimensions TO-252 3L (DPAK) Figure 21. TO252 (D-PAK), Molded, 3 Lead, Option AA&AB Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
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