Datasheet

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FDD6635 Rev. C2(W)

www.fairchildsemi.com

FDD6635

35V N-Channel PowerTrench

MOSFET

General Description

This N-Channel MOSFET has been produced using

Fairchild Semiconductor’s proprietary PowerTrench

technology to deliver low Rdson and optimized Bvdss

capability to offer superior performance benefit in the

applications.

Applications

• Inverter

• Power Supplies

Features

• 59 A, 35 V R

DS(ON)

= 10 mΩ @ V

= 10 V

DS(ON)

= 13 mΩ @ V

= 4.5 V

• Fast Switching

• RoHS compliant

TO-252

D-PAK

(TO-252)

Absolute Maximum Ratings T

=25

C unless otherwise noted

Symbol Parameter Ratings Units

DSS

Drain-Source Voltage 35 V

DS(Avalanche)

Drain-Source Avalanche Voltage (maximum) (Note 4) 40 V

GSS

Gate-Source Voltage

±20

Continuous Drain Current @T

=25°C (Note 3) 59 A

=25°C (Note 1a) 15

Pulsed (Note 1a) 100

Single Pulse Avalanche Energy (Note 5) 113 mJ

Power Dissipation @T

=25°C (Note 3) 55

=25°C (Note 1a) 3.8

=25°C (Note 1b) 1.6

, T

STG

Operating and Storage Junction Temperature Range –55 to +150

°C

Thermal Characteristics

θJC

Thermal Resistance, Junction-to-Case

(Note 1) 2.7

°C/W

θJA

Thermal Resistance, Junction-to-Ambient

(Note 1a) 40

°C/W

θJA

Thermal Resistance, Junction-to-Ambient

(Note 1b) 96

°C/W

Package Marking and Ordering Information

Device Marking Device Package Reel Size Tape width Quantity

FDD6635 FDD6635 D-PAK (TO-252) 13’’ 12mm 2500 units

FDD6635 35V N-Channel PowerTrench

MOSFET

February 2007

Summary of content (8 pages)

PAGE 1
FDD6635 tm 35V N-Channel PowerTrench® MOSFET General Description Features This N-Channel MOSFET has been produced using • 59 A, 35 V Fairchild Semiconductor’s proprietary PowerTrench technology to deliver low Rdson and optimized Bvdss RDS(ON) = 10 mΩ @ VGS = 10 V RDS(ON) = 13 mΩ @ VGS = 4.5 V capability to offer superior performance benefit in the applications.
PAGE 2
Symbol Parameter TA = 25°C unless otherwise noted Test Conditions Min Typ Max Units Off Characteristics(Note 2) ID = 250 μA 35 V BVDSS ΔBVDSS ΔTJ IDSS Drain–Source Breakdown Voltage Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current VDS = 28 V, VGS = 0 V 1 μA IGSS Gate–Body Leakage VGS = ±20 V, VDS = 0 V ±100 nA 3 V On Characteristics VGS(th) ΔVGS(th) ΔTJ RDS(on) gFS VGS = 0 V, ID = 250 μA, Referenced to 25°C 32 mV/°C (Note 2) Gate Threshold Voltage Gate
PAGE 3
Symbol TA = 25°C unless otherwise noted Parameter Test Conditions Min Typ Max Units Drain–Source Diode Characteristics VSD trr Drain–Source Diode Forward Voltage Diode Reverse Recovery Time Qrr Diode Reverse Recovery Charge VGS = 0 V, IS = 15 A IF = 15 A, diF/dt = 100 A/µs 0.8 (Note 2) 1.2 V 26 ns 16 nC Notes: 1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins.
PAGE 4
80 2.4 VGS=10V RDS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE 4.0V 70 ID, DRAIN CURRENT (A) 6.0V 4.5V 60 3.5V 50 40 30 20 3.0V 10 2.2 2 VGS = 3.5V 1.8 1.6 4.0V 1.4 4.5V 5.0V 1.2 6.0V 0.8 0 0 0.5 1 1.5 2 2.5 0 3 10 20 Figure 1. On-Region Characteristics 40 50 60 70 80 Figure 2. On-Resistance Variation with Drain Current and Gate Voltage 1.8 0.029 ID = 7.5A ID = 15A VGS = 10V 1.
PAGE 5
2000 ID = 15A VDS = 10V f = 1MHz VGS = 0 V 15V 1600 8 CAPACITANCE (pF) VGS, GATE-SOURCE VOLTAGE (V) 10 20V 6 4 CISS 1200 800 COSS 2 400 0 0 CRSS 0 5 10 15 20 25 0 30 5 Figure 7. Gate Charge Characteristics 20 25 30 P(pk), PEAK TRANSIENT POWER (W) 100 RDS(ON) LIMIT 100µs 100 1ms 10ms 100ms 10 10s 1s DC 1 VGS = 10V SINGLE PULSE RθJA = 96oC/W 0.1 TA = 25oC 0.01 0.01 0.1 1 10 SINGLE PULSE RθJA = 96°C/W TA = 25°C 80 60 40 20 0 0.01 100 0.
PAGE 6
r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 1 D = 0.5 RθJA(t) = r(t) * RθJA RθJA = 96 °C/W 0.2 0.1 0.1 0.05 P(pk) 0.02 t1 0.0 t2 0.01 TJ - TA = P * RθJA(t) Duty Cycle, D = t1 / t2 SINGLE PULSE 0.001 0.001 0.01 0.1 1 10 100 1000 t1, TIME (sec) Figure 13. Transient Thermal Response Curve Thermal characterization performed using the conditions described in Note 1b. Transient thermal response will change depending on the circuit board design. FDD6635 Rev. C2(W) www.
PAGE 7
L VDS BVDSS tP VGS RGEN + DUT VDD VDD - 0V VGS VDS IAS IAS tp vary tP to obtain required peak IAS 0.01Ω tAV Figure 14. Unclamped Inductive Load Test Circuit Figure 15. Unclamped Inductive Waveforms Drain Current Regulator Same type as DUT + - 10μF QG 10V 50kΩ 10V + 1μF QGD QGS VGS VDD - VGS DUT Charge, (nC) Ig(REF) Figure 16. Gate Charge Test Circuit VDS RL tON tOFF td(ON) VDS + VGS RGEN Figure 17.
PAGE 8
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