Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFDD6637, MOSFET

August 2006

2006 Fairchild Semiconductor Corporation

FDD6637 Rev C2(W)

www.fairchildsemi.com

FDD6637

35V P-Channel PowerTrench



MOSFET

General Description

This P-Channel MOSFET has been produced using

Fairchild Semiconductor’s proprietary PowerTrench

technology to deliver low Rdson and optimized Bvdss

capability to offer superior performance benefit in the

applications.

Applications

• Inverter

• Power Supplies

Features

• –55 A, –35 V R

DS(ON)

= 11.6 mΩ @ V

= –10 V

DS(ON)

= 18 mΩ @ V

= –4.5 V

• High performance trench technology for extremely

low R

DS(ON)

• RoHS Compliant

TO-252

D-PAK

(TO-252)

Absolute Maximum Ratings T

=25

C unless otherwise noted

Symbol Parameter Ratings Units

DSS

Drain-Source Voltage –35 V

DS(Avalanche)

Drain-Source Avalanche Voltage (maximum) (Note 4) –40 V

GSS

Gate-Source Voltage

±25

Continuous Drain Current @T

=25°C (Note 3) –55

=25°C (Note 1a) –13

Pulsed (Note 1a) –100

Power Dissipation @T

=25°C (Note 3) 57

=25°C (Note 1a) 3.1

=25°C (Note 1b) 1.3

, T

STG

Operating and Storage Junction Temperature Range –55 to +150

°C

Thermal Characteristics

θJC

Thermal Resistance, Junction-to-Case (Note 1) 2.2

θJA

Thermal Resistance, Junction-to-Ambient (Note 1a) 40

θJA

Thermal Resistance, Junction-to-Ambient (Note 1b) 96

°C/W

Package Marking and Ordering Information

Device Marking Device Package Reel Size Tape width Quantity

FDD6637 FDD6637 D-PAK (TO-252) 13’’ 12mm 2500 units

FDD6637

35V P

Channel PowerTrench



MOSFET

Summary of content (8 pages)

PAGE 1
FDD6637 35V P-Channel PowerTrench MOSFET General Description Features This P-Channel MOSFET has been produced using • –55 A, –35 V Fairchild Semiconductor’s proprietary PowerTrench RDS(ON) = 11.6 mΩ @ VGS = –10 V RDS(ON) = 18 mΩ @ VGS = –4.5 V technology to deliver low Rdson and optimized Bvdss • High performance trench technology for extremely capability to offer superior performance benefit in the low RDS(ON) applications.
PAGE 2
Symbol Parameter T A = 25°C unless otherwise noted Test Conditions Min Typ Max Units Drain-Source Avalanche Ratings EAS IAS Drain-Source Avalanche Energy (Single Pulse) Drain-Source Avalanche Current VDD = -35 V, ID= -11 A, L=1mH 61 mJ –14 A Off Characteristics(Note 2) IDSS Drain–Source Breakdown Voltage Zero Gate Voltage Drain Current VDS = –28 V, IGSS Gate–Body Leakage VGS = ±25 V, BVDSS On Characteristics VGS = 0 V, ID = –250 µA –35 V VGS = 0 V VDS = 0 V –1 µA ±100 nA –3 11
PAGE 3
Symbol Parameter T A = 25°C unless otherwise noted Test Conditions Min Typ Max Units –0.8 –1.2 Drain–Source Diode Characteristics VSD trr Drain–Source Diode Forward Voltage Diode Reverse Recovery Time Qrr Diode Reverse Recovery Charge VGS = 0 V, IS = –14 A IF = –14 A, (Note 2) diF/dt = 100 A/µs V 28 ns 15 nC Notes: 1.
PAGE 4
100 2.4 -6.0V VGS = -3.5V -5.0V NORMALIZED DRAIN-SOURCE ON-RESISTANCE VGS = -10V -4.5V -I D, DRAIN CURRENT (A) 80 -4.0V 60 -3.5V 40 20 -3.0V 0 1 2 3 -VD S, DRAIN-SOURCE VOLTAGE (V) 1.8 -4.0V 1.6 -4.5V -5.0V 1.4 -6.0V 1.2 -8.0V -10V 1 4 0 Figure 1. On-Region Characteristics 20 40 60 -I D, DRAIN CURRENT (A) 80 100 Figure 2. On-Resistance Variation with Drain Current and Gate Voltage 0.05 1.
PAGE 5
3200 I D = -14A VDS = 10V f = 1MHz VGS = 0 V 30V 8 CAPACITANCE (pF) -VGS, GATE-SOURCE VOLTAGE (V) 10 20V 6 4 2400 C iss 1600 C oss 800 2 C rss 0 0 0 10 20 30 Qg, GATE CHARGE (nC) 40 50 0 Figure 7. Gate Charge Characteristics 30 P(pk), PEAK TRANSIENT POWER (W) 100 100µs 1ms 10ms 100ms 1s 100 -I D , DRAIN CURRENT (A) 10 15 20 25 VD S, DRAIN TO SOURCE VOLTAGE (V) Figure 8. Capacitance Characteristics 1000 R DS(ON) LIMIT 10 10s DC 1 VGS = -10V SINGLE PULSE o R θJA = 96 C/W 0.
PAGE 6
r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 1 D = 0.5 Rθ JA(t) = r(t) * RθJA Rθ JA = 96 °C/W 0.2 0.1 0.1 0.05 P(pk) 0.02 0.01 t1 0.01 t2 T J - T A = P * Rθ JA (t) Duty Cycle, D = t1 / t 2 SINGLE PULSE 0.001 0.001 0.01 0.1 1 10 100 1000 t 1, TIME (sec) Figure 13. Transient Thermal Response Curve Thermal characterization performed using the conditions described in Note 1b. Transient thermal response will change depending on the circuit board design. FDD6637 Rev. C2(W) www.
PAGE 7
L VDS BVDSS tP VG RGEN DUT VDD VDD + 0V VGS VDS IAS - tp vary tP to obtain required peak IAS IAS 0.01Ω tAV Figure 14. Unclamped Inductive Load Test Circuit Figure 15. Unclamped Inductive Waveforms Drain Current Regulator Same type as DUT + 10µF QG 10V 50kΩ 10V - 1µF + QGD Q GS VGS VDD VG DUT Charge, (nC) Ig(REF) Figure 16. Gate Charge Test Circuit VDS RL t ON DUT VDS Pulse Width ≤ 1µs Duty Cycle ≤ 0.1% Figure 18.
PAGE 8
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