Datasheet

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February 2014

FDD8424H Dual N & P-Channel PowerTrench

MOSFET

FDD8424H Rev.C2

www.fairchildsemi.com

FDD8424H

Dual N & P-Channel PowerTrench

MOSFET

N-Channel: 40V, 20A, 24mΩ P-Channel: -40V, -20A, 54mΩ

Features

Q1: N-Channel

 Max r

DS(on)

= 24mΩ at V

= 10V, I

= 9.0A

 Max r

DS(on)

= 30mΩ at V

= 4.5V, I

= 7.0A

Q2: P-Channel

 Max r

DS(on)

= 54mΩ at V

= -10V, I

= -6.5A

 Max r

DS(on)

= 70mΩ at V

= -4.5V, I

= -5.6A

 Fast switching speed

 RoHS Compliant

General Description

These dual N and P-Channel enhancement mode Power

MOSFETs are produced using Fairchild Semiconductor’s

advanced PowerTrench- process that has been especially

tailored to minimize on-state resistance and yet maintain

superior switching performance.

Application

 Inverter

 H-Bridge

MOSFET Maximum Ratings T

= 25°C unless otherwise noted

Thermal Characteristics

Package Marking and Ordering Information

Symbol Parameter Q1 Q2 Units

Drain to Source Voltage 40 -40 V

Gate to Source Voltage ±20 ±20 V

Drain Current - Continuous (Package Limited) 20 -20

- Continuous (Silicon Limited) T

= 25°C 26 -20

- Continuous T

= 25°C 9.0 -6.5

- Pulsed 55 -40

Power Dissipation for Single Operation T

= 25°C (Note 1) 30 35

W T

= 25°C (Note 1a) 3.1

= 25°C (Note 1b) 1.3

Single Pulse Avalanche Energy (Note 3) 29 33 mJ

, T

STG

Operating and Storage Junction Temperature Range -55 to +150 °C

θJC

Thermal Resistance, Junction to Case, Single Operation for Q1 (Note 1) 4.1

°C/W

θJC

Thermal Resistance, Junction to Case, Single Operation for Q2 (Note 1) 3.5

Device Marking Device Package Reel Size Tape Width Quantity

FDD8424H FDD8424H TO-252-4L 13” 12mm 2500 units

Dual DPAK 4L

D1/D2

N-Channel P-Channel

D1 D2

Summary of content (11 pages)

PAGE 1
FDD8424H Dual N & P-Channel PowerTrench® MOSFET N-Channel: 40V, 20A, 24mΩ P-Channel: -40V, -20A, 54mΩ Features General Description Q1: N-Channel These dual N and P-Channel enhancement Max rDS(on) = 24mΩ at VGS = 10V, ID = 9.0A MOSFETs are produced using Fairchild Semiconductor’s mode Power advanced PowerTrench- process that has been especially Max rDS(on) = 30mΩ at VGS = 4.5V, ID = 7.0A tailored to minimize on-state resistance and yet maintain superior switching performance.
PAGE 2
Symbol Parameter Test Conditions Type Min 40 -40 Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = 250μA, VGS = 0V ID = -250μA, VGS = 0V Q1 Q2 ΔBVDSS ΔTJ Breakdown Voltage Temperature Coefficient ID = 250μA, referenced to 25°C ID = -250μA, referenced to 25°C Q1 Q2 IDSS Zero Gate Voltage Drain Current VDS = 32V, VGS = 0V VDS = -32V, VGS = 0V Q1 Q2 1 -1 μA IGSS Gate to Source Leakage Current VGS = ±20V, VDS = 0V Q1 Q2 ±100 ±100 nA nA 3 -3 V V 34 -32
PAGE 3
Symbol Parameter Test Conditions Type Min Typ Max Units Q1 Q2 20 -20 A 55 -40 A Drain-Source Diode Characteristics IS Maximum Continuous Drain to Source Diode Forward Current ISM Maximum Pulsed Drain to Source Diode Forward Current (Note 2) Q1 Q2 VSD Source to Drain Diode Forward Voltage VGS = 0V, IS = 9.0A VGS = 0V, IS = -6.5A (Note 2) (Note 2) Q1 Q2 0.87 0.88 1.2 -1.2 V trr Reverse Recovery Time Q1 Q2 25 29 38 44 ns Qrr Reverse Recovery Charge Q1 IF = 9.
PAGE 4
3.0 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 60 VGS = 4.0V ID, DRAIN CURRENT (A) 50 VGS = 10V PULSE DURATION = 80μs DUTY CYCLE = 0.5%MAX 40 VGS = 4.5V 30 VGS = 3.5V 20 10 VGS = 3.0V 0 0 1 2 3 VGS = 3.0V 2.5 2.0 VGS = 4.5V 1.5 1.0 VGS = 10V 0.5 4 0 10 rDS(on), DRAIN TO 1.0 0.8 -50 -25 0 25 50 75 SOURCE ON-RESISTANCE (mΩ) NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 1.2 ID = 9A 60 PULSE DURATION = 80μs DUTY CYCLE = 0.
PAGE 5
2000 ID = 9A Ciss 1000 8 CAPACITANCE (pF) VGS, GATE TO SOURCE VOLTAGE(V) 10 6 VDD = 20V VDD = 15V 4 VDD = 25V Coss 100 2 f = 1MHz VGS = 0V 30 0.1 0 0 4 8 12 16 1 Figure 7. Gate Charge Characteristics 40 Figure 8. Capacitance vs Drain to Source Voltage 30 ID, DRAIN CURRENT (A) 30 IAS, AVALANCHE CURRENT(A) 10 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE(nC) TJ = 25oC 10 TJ = 125oC 25 Limited by Package 20 VGS = 10V 15 10 VGS = 4.5V 5 o RθJC = 4.1 C/W 1 0.001 0.01 0.
PAGE 6
2 NORMALIZED THERMAL IMPEDANCE, ZθJC 1 0.1 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 0.01 0.005 -5 10 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC x RθJC + TC SINGLE PULSE RθJC = 4.1oC/W -4 10 -3 -2 10 10 -1 10 0 10 1 10 t, RECTANGULAR PULSE DURATION (s) Figure 13. Transient Thermal Response Curve ©2013 Fairchild Semiconductor Corporation FDD8424H Rev.C2 6 www.fairchildsemi.
PAGE 7
3.0 VGS = -10V PULSE DURATION = 80μs DUTY CYCLE = 0.5%MAX 30 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE -ID, DRAIN CURRENT (A) 40 VGS = -4.5V VGS = -4V 20 VGS = -3.5V 10 VGS = -3V 0 0 1 2 3 VGS = -3V PULSE DURATION = 80μs DUTY CYCLE = 0.5%MAX 2.5 VGS = -3.5V VGS = -4V 2.0 VGS = -4.5V 1.5 VGS = -10V 1.0 0.5 0 4 10 -VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 14. On- Region Characteristics 40 160 ID = -6.5A VGS = -10V rDS(on), DRAIN TO 1.4 1.2 1.0 0.8 0.
PAGE 8
2000 Ciss ID = -6.5A 8 1000 VDD = -15V CAPACITANCE (pF) -VGS, GATE TO SOURCE VOLTAGE(V) 10 VDD = -20V 6 VDD = -25V 4 Coss Crss 100 2 f = 1MHz VGS = 0V 30 0.1 0 0 4 8 12 16 20 1 Figure 21. Capacitance vs Drain to Source Voltage Figure 20. Gate Charge Characteristics 25 10 -ID, DRAIN CURRENT (A) -IAS, AVALANCHE CURRENT(A) 30 TJ = 25oC TJ = 125oC 20 VGS = -10V 15 10 VGS = -4.5V 5 o RθJC = 3.5 C/W 1 0.001 0.01 0.
PAGE 9
2 NORMALIZED THERMAL IMPEDANCE, ZθJC 1 0.1 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 0.01 0.005 -5 10 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC x RθJC + TC SINGLE PULSE o RθJC = 3.5 C/W -4 10 -3 -2 10 10 -1 10 0 10 1 10 t, RECTANGULAR PULSE DURATION (s) Figure 26. Transient Thermal Response Curve ©2013 Fairchild Semiconductor Corporation FDD8424H Rev.C2 9 www.fairchildsemi.
PAGE 10
FDD8424H Dual N & P-Channel PowerTrench® MOSFET Dimensional Outline and Pad Layout ©2013 Fairchild Semiconductor Corporation FDD8424H Rev.C2 10 www.fairchildsemi.
PAGE 11
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