Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFDD86113LZ, MOSFET

June 2013

FDD86113LZ N-Channel Shielded Gate PowerTrench

MOSFET

FDD86113LZ Rev. C1

FDD86113LZ

N-Channel Shielded Gate PowerTrench

MOSFET

100 V, 5.5 A, 104 mΩ

Features

 Shielded Gate MOSFET Technology

 Max r

DS(on)

= 104 mΩ at V

= 10 V, I

= 4.2 A

 Max r

DS(on)

= 156 mΩ at V

= 4.5 V, I

= 3.4 A

 HBM ESD protection level > 6 kV typical (Note 4)

 High performance trench technology for extremely low rDS(on)

 High power and current handling capability in a widely used

surface mount package

 100% UIL Tested

 RoHS Compliant

General Description

This N-Channel logic Level MOSFETs are produced using

Fairchild Semiconductor‘s advanced PowerTrench

process

that incorporates Shielded Gate technology. This process has

been optimized for the on-state resistance and yet maintain

superior switching performance. G-S zener has been added to

enhance ESD voltage level.

Application

 DC-DC conversion

TO-252

D-PAK

(TO-252)

MOSFET Maximum Ratings T

= 25 °C unless otherwise noted

Thermal Characteristics

Package Marking and Ordering Information

Symbol Parameter Ratings Units

Drain to Source Voltage 100 V

Gate to Source Voltage ±20 V

Drain Current -Continuous T

= 25 °C 5.5

A -Continuous T

A = 25 °C (Note 1a) 4.2

-Pulsed 15

Single Pulse Avalanche Energy (Note 3) 12 mJ

Power Dissipation T

= 25 °C 29

Power Dissipation T

= 25 °C (Note 1a) 3.1

, T

STG

Operating and Storage Junction Temperature Range -55 to +150 °C

θJC

Thermal Resistance, Junction to Case (Note 1) 4.3

°C/W

θJA

Thermal Resistance, Junction to Ambient (Note 1a) 96

Device Marking Device Package Reel Size Tape Width Quantity

FDD86113LZ FDD86113LZ D-PAK(TO-252) 13 ’’ 12 mm 2500 units

Summary of content (6 pages)

PAGE 1
FDD86113LZ N-Channel Shielded Gate PowerTrench® MOSFET 100 V, 5.5 A, 104 mΩ Features General Description Shielded Gate MOSFET Technology This N-Channel logic Level MOSFETs are produced using Fairchild Semiconductor‘s advanced PowerTrench® process that incorporates Shielded Gate technology. This process has been optimized for the on-state resistance and yet maintain superior switching performance. G-S zener has been added to enhance ESD voltage level. Max rDS(on) = 104 mΩ at VGS = 10 V, ID = 4.
PAGE 2
Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V ΔBVDSS ΔTJ Breakdown Voltage Temperature Coefficient ID = 250 μA, referenced to 25 °C IDSS Zero Gate Voltage Drain Current VDS = 80 V, VGS = 0 V 1 μA IGSS Gate to Source Leakage Current VGS = ±20 V, VDS = 0 V ±10 μA 3 V 100 V 72 mV/°C On Characteristics VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250 μA ΔVGS(th) ΔTJ Gate to Source
PAGE 3
4 ID, DRAIN CURRENT (A) VGS = 10 V NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 15 VGS = 4.5 V 12 VGS = 3.5 V 9 VGS = 3 V 6 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 3 VGS = 2.5 V 0 0 1 2 3 4 5 VGS = 2.5 V VGS = 3 V 3 VGS = 3.5 V 2 VGS = 4.5 V 1 0 0 3 VDS, DRAIN TO SOURCE VOLTAGE (V) 12 15 400 ID = 4.2 A VGS = 10 V 1.8 rDS(on), DRAIN TO 1.6 1.4 1.2 1.0 0.8 0.6 -75 -50 SOURCE ON-RESISTANCE (mΩ) NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 9 Figure 2.
PAGE 4
VGS, GATE TO SOURCE VOLTAGE (V) 10 1000 ID = 4.2 A VDD = 25 V Ciss CAPACITANCE (pF) 8 VDD = 50 V 6 VDD = 75 V 4 100 10 2 0 Coss Crss f = 1 MHz VGS = 0 V 0 1 2 3 1 0.1 4 Figure 7. Gate Charge Characteristics 10 12 o RθJC = 4.3 C/W ID, DRAIN CURRENT (A) 5 IAS, AVALANCHE CURRENT (A) 100 Figure 8. Capacitance vs Drain to Source Voltage 6 4 TJ = 25 oC 3 TJ = 100 oC 2 TJ = 125 oC 10 VGS = 10 V 8 VGS = 4.5 V 6 4 Limited by Package 2 1 0.01 0.
PAGE 5
2000 P(PK), PEAK TRANSIENT POWER (W) SINGLE PULSE o 1000 RθJC = 4.3 C/W o TC = 25 C 100 10 -5 10 -4 -3 10 -2 10 -1 10 10 1 t, PULSE WIDTH (sec) Figure 13. Single Pulse Maximum Power Dissipation 2 DUTY CYCLE-DESCENDING ORDER NORMALIZED THERMAL IMPEDANCE, ZθJC 1 0.1 D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC x RθJC + TC SINGLE PULSE o RθJC = 4.3 C/W 0.
PAGE 6
tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.