April 2008 FDD8878 / FDU8878 N-Channel PowerTrench® MOSFET tm 30V, 40A, 15mΩ Features rDS(ON) = 15mΩ, VGS = 10V, ID = 35A rDS(ON) = 18.5mΩ, VGS = 4.5V, ID = 35A High performance trench technology for extremely low General Description This N-Channel MOSFET has been designed specifically to improve the overall efficiency of DC/DC converters using either synchronous or conventional switching PWM controllers. It has been optimized for low gate charge, low r DS(ON) and fast switching speed.
Symbol VDSS Drain to Source Voltage Parameter Ratings 30 Units V VGS Gate to Source Voltage ±20 V 40 A Continuous (TC = 25 C, VGS = 4.5V) (Note 1) 36 A Continuous (Tamb = 25oC, VGS = 10V, with RθJA = 52oC/W) 11 A Drain Current Continuous (TC = 25oC, VGS = 10V) (Note 1) o ID Pulsed E AS Figure 4 A 25 mJ Single Pulse Avalanche Energy (Note 2) Power dissipation PD Derate above 25oC TJ, TSTG Operating and Storage Temperature 40 W 0.
CISS Input Capacitance COSS Output Capacitance CRSS Reverse Transfer Capacitance RG Gate Resistance Qg(TOT) Total Gate Charge at 10V - 880 - - 195 - pF - 110 - pF VGS = 0.5V, f = 1MHz - 3.
50 CURRENT LIMITED BY PACKAGE 1.0 40 ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER 1.2 0.8 0.6 0.4 VGS = 10V 30 VGS = 4.5V 20 10 0.2 0 0 25 50 75 100 150 125 0 175 25 50 75 TC , CASE TEMPERATURE (o C) 100 125 150 175 TC, CASE TEMPERATURE (oC) Figure 1. Normalized Power Dissipation vs Case Temperature Figure 2. Maximum Continuous Drain Current vs Case Temperature 2 ZθJC, NORMALIZED THERMAL IMPEDANCE 1 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM 0.
1000 500 100 10µs 10 100µs 1 IAS, AVALANCHE CURRENT (A) ID, DRAIN CURRENT (A) OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 1ms 10ms SINGLE PULSE TJ = MAX RATED TC = 25oC If R = 0 tAV = (L)(I AS)/(1.3*RATED BVDSS - VDD) If R ≠ 0 tAV = (L/R)ln[(I AS*R)/(1.3*RATED BVDSS - VDD) +1] 100 STARTING T J = 25o C 10 STARTING TJ = 150o C DC 1 0.01 0.1 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 60 0.1 1 tAV, TIME IN AVALANCHE (ms) NOTE: Refer to Fairchild Application Notes AN7514 and AN7515 Figure 5.
1.2 1.10 ID = 250µA NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE NORMALIZED GATE THRESHOLD VOLTAGE VGS = VDS, ID = 250µA 1.0 0.8 0.6 0.4 -80 -40 0 40 80 120 160 1.05 1.00 0.95 0.90 -80 200 -40 TJ, JUNCTION TEMPERATURE (oC) Figure 11. Normalized Gate Threshold Voltage vs Junction Temperature 80 120 160 200 10 VDD = 15V VGS , GATE TO SOURCE VOLTAGE (V) CISS = CGS + CGD 1000 C, CAPACITANCE (pF) 40 Figure 12.
VDS BVDSS tP L VDS VARY tP TO OBTAIN REQUIRED PEAK IAS IAS + RG VDD VDD - VGS DUT tP IAS 0V 0 0.01Ω tAV Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms VDS VDD Qg(TOT) VDS L VGS VGS = 10V VGS Qg(5) + Qgs2 VDD VGS = 5V DUT VGS = 1V Ig(REF) 0 Qg(TH) Qgs Qgd Ig(REF) 0 Figure 17. Gate Charge Test Circuit Figure 18.
The maximum rated junction temperature, TJM , and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM , in an application. Therefore the application’s ambient temperature, TA (oC), and thermal resistance RθJA (oC/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part. RθJA = 33.32+ 23.84/(0.268+Area) EQ.2 RθJA = 33.
.SUBCKT FDD8878 2 1 3 ; rev February 2004 Ca 12 8 8.6e-10 Cb 15 14 7.2e-10 Cin 6 8 8e-10 LDRAIN DPLCAP 10 Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD Dplcap 10 5 DplcapMOD RLDRAIN RSLC1 51 5 51 EVTHRES + 19 8 + LGATE GATE 1 ESLC 11 + 17 EBREAK 18 - 50 RDRAIN 6 8 ESG DBREAK + RSLC2 Ebreak 11 7 17 18 32.97 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1 It 8 17 1 DRAIN 2 5 EVTEMP RGATE + 18 22 9 20 21 16 DBODY MWEAK 6 MMED MSTRO RLGATE Lgate 1 9 5.
rev February 2004 template FDD8878 n2,n1,n3 =m_temp electrical n2,n1,n3 number m_temp=25 { var i iscl dp..model dbodymod = (isl=2.6e-12,ikf=8,nl=1.01,rs=6.4e-3,trs1=8e-4,trs2=2e-7,cjo=3.4e-10,m=0.53,tt=1e-17,xti=2) dp..model dbreakmod = (rs=1.4,trs1=1e-3,trs2=-5e-6) dp..model dplcapmod = (cjo=3.4e-10,isl=10e-30,nl=10,m=0.39) m..model mmedmod = (type=_n,vto=1.75,kp=7,is=1e-30, tox=1) m..model mstrongmod = (type=_n,vto=2.2,kp=100,is=1e-30, tox=1) m..model mweakmod = (type=_n,vto=1.45,kp=0.
th JUNCTION REV 23 February 2004 FDD8878T CTHERM1 TH 6 3.5e-4 CTHERM2 6 5 5e-4 CTHERM3 5 4 2.5e-3 CTHERM4 4 3 2.7e-3 CTHERM5 3 2 5e-3 CTHERM6 2 TL 1e-2 RTHERM1 CTHERM1 6 RTHERM1 TH 6 2.9e-1 RTHERM2 6 5 3.5e-1 RTHERM3 5 4 4.5e-1 RTHERM4 4 3 5.2e-1 RTHERM5 3 2 6.9e-1 RTHERM6 2 TL 7e-1 RTHERM2 CTHERM2 5 SABER Thermal Model SABER thermal model FDD8878T template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 =3.5e-4 ctherm.ctherm2 6 5 =5e-4 ctherm.ctherm3 5 4 =2.5e-3 ctherm.ctherm4 4 3 =2.
TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidianries, and is not intended to be an exhaustive list of all such trademarks.
