Datasheet

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FDFMA2N028Z Integrated N-Channel PowerTrench

MOSFET and Schottky Diode

FDFMA2N028Z Rev.B www.fairchildsemi.com

FDFMA2N028Z

Integrated N-Channel PowerTrench

MOSFET and Schottky Diode

20V, 3.7A, 68mΩ

Features

MOSFET

 Max r

DS(on)

= 68mΩ at V

= 4.5V, I

= 3.7A

 Max r

DS(on)

= 86mΩ at V

= 2.5V, I

= 3.3A

Schottky

 V

< 0.37V @ 500mA

 Low profile - 0.8 mm maximum - in the new package MicroFET

2x2 mm

 RoHS Compliant

General Description

This device is designed specifically as a single package solution

for a boost topology in cellular handset and other ultra-portable

applications. It features a MOSFET with low on-state resistance,

and an independently connected schottky diode with low forward

voltage.

The MicroFET 2x2 package offers exceptional thermal

per

formance for its physical size and is well suited to swit

ching

and linear mode applications.

Application

 DC - DC Conversion

MOSFET Maximum Ratings

= 25°C unless otherwise noted

Thermal Characteristics

Package Marking and Ordering Information

Symbol Parameter Ratings Units

Drain to Source Voltage 20 V

Gate to Source Voltage ±12 V

Drain Current -Continuous (Note 1a) 3.7

-Pulsed 6

Power Dissipation (Note 1a) 1.4

Power Dissipation (Note 1b) 0.7

, T

STG

Operating and Storage Junction Temperature Range -55 to +150 °C

Schottky Repetitive Peak Reverse Voltage 20 V

Schottky Average Forward Current 2 A

θJA

Thermal Resistance, Junction to Ambient (Note 1a) 86

°C/W

θJA

Thermal Resistance, Junction to Ambient (Note 1b) 173

θJA

Thermal Resistance, Junction to Ambient (Note 1c) 86

θJA

Thermal Resistance, Junction to Ambient (Note 1d) 140

Device Marking Device Package Reel Size Tape Width Quantity

.N28 FDFMA2N028Z MicroFET 2X2 7’’ 8mm 3000 units

MicroFET 2X2

Pin 1

 HBM ESD protection level > 2kV (Note 3)

July 2014

Summary of content (8 pages)

PAGE 1
FDFMA2N028Z Integrated N-Channel PowerTrench® MOSFET and Schottky Diode 20V, 3.7A, 68mΩ Features General Description MOSFET This device is designed specifically as a single package solution for a boost topology in cellular handset and other ultra-portable applications. It features a MOSFET with low on-state resistance, and an independently connected schottky diode with low forward voltage. Max rDS(on) = 68mΩ at VGS = 4.5V, ID = 3.7A Max rDS(on) = 86mΩ at VGS = 2.5V, ID = 3.
PAGE 2
Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = 250μA, VGS = 0V ΔBVDSS ΔTJ Breakdown Voltage Temperature Coefficient 20 V ID = 250μA, referenced to 25°C IDSS Zero Gate Voltage Drain Current VDS = 16V, VGS = 0V 1 μA IGSS Gate to Source Leakage Current VGS = ±12V, VDS = 0V ±10 μA 1.
PAGE 3
Notes: 1: RθJA is determined with the device mounted on a 1in2 pad 2 oz. copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθJA is determined by the user's board design. (a) MOSFET RθJA = 86oC/W when mounted on a 1in2 pad of 2 oz copper, 1.5” x 1.5” x 0.062” thick PCB. (b) MOSFET RθJA = 173oC/W when mounted on a minimum pad of 2 oz copper. (c) Schottky RθJA = 86oC/W when mounted on a 1in2 pad of 2 oz copper, 1.5” x 1.5” x 0.062” thick PCB.
PAGE 4
2.0 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 6 ID, DRAIN CURRENT (A) 5 VGS = 4.5V 4 VGS = 3.0V VGS = 2.5V 3 2 VGS = 2.0V PULSE DURATION = 300μs DUTY CYCLE = 2%MAX 1 VGS = 1.5V 0 0.0 0.2 0.4 0.6 0.8 1.0 VDS, DRAIN TO SOURCE VOLTAGE (V) 1.2 1.6 1.4 1.0 0.8 -25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (oC) 150 Figure 3. Normalized On- Resistance vs Junction Temperature VDD=5V PULSE DURATION = 300μs DUTY CYCLE = 2%MAX 4 3 TJ 2 = 125oC TJ = 25oC 1 0 0.5 TJ = -55oC 1.0 1.5 2.
PAGE 5
1000 VGS, GATE TO SOURCE VOLTAGE(V) 10 ID = 3.7A Ciss VDD = 15V VDD = 5V 6 CAPACITANCE (pF) 8 4 VDD = 10V 2 0 2 4 6 Qg, GATE CHARGE(nC) 8 Crss f = 1MHz VGS = 0V 10 0.1 10 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 7. Gate Charge Characteristics Figure 8. Capacitance Characteristics 20 10 50 P(PK), PEAK TRANSIENT POWER (W) ID, DRAIN CURRENT (A) 0 Coss 100 rDS(on) LIMIT 100us 1ms 1 10ms VGS=4.5V 0.1 100ms SINGLE PULSE R 1s 10s DC o =173 θJA C/W o TA = 25 C 0.01 0.
PAGE 6
2 NORMALIZED THERMAL IMPEDANCE, ZθJA 1 0.1 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 SINGLE PULSE NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA 0.01 0.005 -4 10 -3 10 -2 10 -1 0 10 10 1 10 2 10 3 10 t, RECTANGULAR PULSE DURATION (s) Figure 13. Transient Thermal Response Curve FDFMA2N028Z Rev.B2 6 www.fairchildsemi.
PAGE 7
FDFMA2N028Z Integrated N-Channel PowerTrench® MOSFET and Schottky Diode Dimensional Outline and Pad Layout Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
PAGE 8
tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.