Datasheet

©2010 Fairchild Semiconductor Corporation
FDG1024NZ Rev.C
www.fairchildsemi.com
1
FDG1024NZ Dual N-Channel Power Trench
®
MOSFET
June 2010
S1
SC70-6
S1
G1
D2
D1
G2
S2
G1
D2
D1
G2
S2
3
2
1
4
5
6
FDG1024NZ
Dual N-Channel PowerTrench
®
MOSFET
20 V, 1.2 A, 175 mΩ
Features
 Max r
DS(on)
= 175 mΩ at V
GS
= 4.5 V, I
D
= 1.2 A
 Max r
DS(on)
= 215 mΩ at V
GS
= 2.5 V, I
D
= 1.0 A
 Max r
DS(on)
= 270 mΩ at V
GS
= 1.8 V, I
D
= 0.9 A
 Max r
DS(on)
= 389 mΩ at V
GS
= 1.5 V, I
D
= 0.8 A
 HBM ESD protection level >2 kV (Note 3)
 Very low level gate drive requirements allowing operation in
1.5 V circuits (V
GS(th)
< 1 V)
 Very small package outline SC70-6
 RoHS Compliant
General Description
This dual N-Channel logic level enhancement mode field effect
transistors are produced using Fairchild’s proprietary, high cell
density, DMOS technology. This very high density process is
especially tailored to minimize on-state resistance. This device
has been designed especially for low voltage applications as a
replacement for bipolar digital transistors and small signal
MOSFETs. Since bias resistors are not required, this dual digital
FET can replace several different digital transistors, with
different bias resistor values.
MOSFET Maximum Ratings T
A
= 25 °C unless otherwise noted
Thermal Characteristics
Package Marking and Ordering Information
Symbol Parameter Ratings Units
V
DS
Drain to Source Voltage 20 V
V
GS
Gate to Source Voltage ±8 V
I
D
-Continuous T
A
= 25°C (Note 1a) 1.2
A
-Pulsed 6
P
D
Power Dissipation T
A
= 25°C (Note 1a) 0.36
W
Power Dissipation T
A
= 25°C (Note 1b) 0.30
T
J
, T
STG
Operating and Storage Junction Temperature Range -55 to +150 °C
R
θJA
Thermal Resistance, Junction to Ambient (Note 1a) 350
°C/W
R
θJA
Thermal Resistance, Junction to Ambient (Note 1b) 415
Device Marking Device Package Reel Size Tape Width Quantity
.4N FDG1024NZ SC70-6 7 ” 8 mm 3000 units