Datasheet

July 1999
FDG6304P
Dual P-Channel, Digital FET
General Description Features
*The pinouts are symmetrical; pin 1 and 4 are interchangeable.
Units inside the carrier can be of either orientation and will not affect the functionality of the device.
Absolute Maximum Ratings T
A
= 25°C unless otherwise noted
Symbol Parameter FDG6304P Units
V
DSS
Drain-Source Voltage -25 V
V
GSS
Gate-Source Voltage -8 V
I
D
Drain/Output Current - Continuous -0.41 A
- Pulsed -1.5
P
D
Maximum Power Dissipation (Note 1) 0.3 W
T
J
,T
STG
Operating and Storage Temperature Range -55 to 150 °C
ESD Electrostatic Discharge Rating MIL-STD-883D
Human Body Model (100 pF / 1500 Ω)
6.0 kV
THERMAL CHARACTERISTICS
R
θ
JA
Thermal Resistance, Junction-to-Ambient (Note 1) 415 °C/W
FDG6304P Rev.E1
-25 V, -0.41 A continuous, -1.5 A peak.
R
DS(ON)
= 1.1 Ω @ V
GS
= -4.5 V,
R
DS(ON)
= 1.5 Ω @ V
GS
= -2.7 V.
Very low level gate drive requirements allowing direct
operation in 3 V circuits (V
GS(th)
< 1.5 V).
Gate-Source Zener for ESD ruggedness
(>6kV Human Body Model).
Compact industry standard SC70-6 surface
mount package.
These dual P-Channel logic level enhancement mode
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This
very high density process is especially tailored to
minimize on-state resistance. This device has been
designed especially for low voltage applications as a
replacement for bipolar digital transistors and small
signal MOSFETs.
SOT-23
SuperSOT
TM
-8
SO-8
SOT-223
SC70-6
SuperSOT
TM
-6
1 or 4
*
6 or 3
5 or 2
4 or 1
*
2 or 5
3 or 6
SC70-6
G1
D2
S1
D1
S2
G2
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