Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFDG6318P, MOSFET

January 2003

2003 Fairchild Semiconductor Corporation

FDG6318P Rev C (W)

FDG6318P

Dual P-Channel, Digital FET

General Description

These dual P-Channel logic level enhancement mode

MOSFET are produced using Fairchild Semiconductor’s

advanced PowerTrench process that has been

especially tailored to minimize on-state resistance. This

device has been designed especially for low voltage

applications as a replacement for bipolar digital

transistors and small signal MOSFETS.

Applications

• Battery management

Features

• –0.5 A, –20 V. R

DS(ON)

= 780 mΩ @ V

= –4.5 V

DS(ON)

= 1200 mΩ @ V

= –2.5 V

• Very low level gate drive requirements allowing direct

operation in 3V circuits (V

GS(th)

< 1.5V).

• Compact industry standard SC70-6 surface mount

package

Pin 1

SC70-6

6 or 3

5 or 2

4 or 1

1 or 4

2 or 5

3 or 6

The pinouts are symmetrical; pin 1 and pin 4 are interchangeable.

Absolute Maximum Ratings

=25

C unless otherwise noted

Symbol Parameter Ratings Units

DSS

Drain-Source Voltage –20 V

GSS

Gate-Source Voltage ±12 V

Drain Current – Continuous

(Note 1)

–0.5 A

– Pulsed –1.8

Power Dissipation for Single Operation

(Note 1)

0.3 W

, T

STG

Operating and Storage Junction Temperature Range –55 to +150

°C

Thermal Characteristics

θJA

Thermal Resistance, Junction-to-Ambient

(Note 1)

415

°C/W

Package Marking and Ordering Information

Device Marking Device Reel Size Tape width Quantity

.38 FDG6318P 7’’ 8mm 3000 units

FDG6318P

Summary of content (5 pages)

PAGE 1
FDG6318P Dual P-Channel, Digital FET General Description Features These dual P-Channel logic level enhancement mode MOSFET are produced using Fairchild Semiconductor’s advanced PowerTrench process that has been especially tailored to minimize on-state resistance. This device has been designed especially for low voltage applications as a replacement for bipolar digital transistors and small signal MOSFETS. • –0.5 A, –20 V. RDS(ON) = 780 mΩ @ VGS = –4.5 V RDS(ON) = 1200 mΩ @ VGS = –2.
PAGE 2
Symbol Parameter TA = 25°C unless otherwise noted Test Conditions Min Typ Max Units Off Characteristics BVDSS ID = –250 µA VGS = 0 V, ∆BVDSS ∆TJ IDSS Drain–Source Breakdown Voltage Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current VDS = –16 V, VGS = 0 V –1 µA IGSS Gate–Body Leakage VGS = ±12 V, VDS = 0 V ±100 nA On Characteristics –20 ID = –250 µA, Referenced to 25°C V –10 mV/°C (Note 2) ID = –250 µA VGS(th) Gate Threshold Voltage VDS = VGS, ∆VGS(th) ∆T
PAGE 3
FDG6318P Typical Characteristics 1.8 1.75 -ID, DRAIN CURRENT (A) -4.5V RDS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE -3.5V VGS = -10.0V -3.0V -6.0V 1.2 -2.5V 0.6 -2.0V VGS = -3.5V 1.5 -4.0V -4.5V -5.0V 1.25 -6.0V -10.0V 1 0.75 0 0 0.5 1 1.5 2 2.5 0 3 0.4 Figure 1. On-Region Characteristics. 1.2 1.6 Figure 2. On-Resistance Variation with Drain Current and Gate Voltage. 1.8 1.4 ID = -0.5A VGS = -4.5V 1.
PAGE 4
FDG6318P Typical Characteristics 120 ID = -0.5A f = 1MHz VGS = 0 V VDS = -5V 8 -10V 6 CAPACITANCE (pF) -VGS, GATE-SOURCE VOLTAGE (V) 10 -15V 4 80 Ciss 40 Coss 2 Crss 0 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 0 4 Qg, GATE CHARGE (nC) 8 12 16 Figure 7. Gate Charge Characteristics. Figure 8. Capacitance Characteristics. 30 10 SINGLE PULSE RθJA = 415oC/W RDS(ON) LIMIT 100µs 24 TA = 25oC 1ms POWER (W) 1 10ms 100ms 1s DC VGS = -4.5V SINGLE PULSE RθJA = 415oC/W 0.
PAGE 5
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