Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFDG6318PZ, MOSFET

January 2003

FDG6318PZ Rev. B

FDG6318PZ

Dual P-Channel, Digital FET

General Description

These dual P-Channel logic level enhancement mode

MOSFET are produced using Fairchild Semiconductor’s

especially tailored to minimize on-state resistance. This

device has been designed especially for bipolar digital

transistors and small signal MOSFETS

Applications

• Battery management

Features

• -0.5A, -20V. r

DS(ON)

= 780mΩ (Max)@ V

= -4.5 V

DS(ON)

= 1200mΩ (Max) @ V

= -2.5 V

• Very low level gate drive requirements allowing direct

operation in 3V circuits (V

GS(TH)

< 1.5V).

• Gate-Source Zener for ESD ruggedness (>1.4kV Human

Body Model).

• Compact industry standard SC-70-6 surface mount

package.

MOSFET Maximum Ratings T

=25°C unless otherwise noted

Thermal Characteristics

Package Marking and Ordering Information

Symbol Parameter Ratings Units

DSS

Drain to Source Voltage -20 V

Gate to Source Voltage ±12 V

Drain Current

-0.5 A

Continuous (T

= 25

C, V

= - 4.5V)

Continuous (T

= 100

C, V

= - 2.5V) -0.3 A

Pulsed Figure 4

Power dissipation 0.3 W

Derate above 25°C 2.4 mW/

, T

STG

Operating and Storage Temperature -55 to 150

ESD

Electrostatic Discharge Rating MIL-STD-883D

Human Body Model ( 100pF / 1500Ω )

1.4 kV

θJA

Thermal Resistance Junction to Ambient (Note 1) 415

C/W

Device Marking Device Package Reel Size Tape Width Quantity

.68 FDG6318PZ SC70-6 7” 8 mm 3000

Pin 1

SC70-6

The pinouts are symmetrical; pin1 and pin 4 are interchangeable.

6or3

5or2

4or1

1or4

2or5

3or6

Summary of content (9 pages)

PAGE 1
FDG6318PZ Dual P-Channel, Digital FET General Description Features These dual P-Channel logic level enhancement mode MOSFET are produced using Fairchild Semiconductor’s especially tailored to minimize on-state resistance. This device has been designed especially for bipolar digital transistors and small signal MOSFETS • -0.5A, -20V. r DS(ON) = 780mΩ (Max)@ VGS = -4.5 V rDS(ON) = 1200mΩ (Max) @ V GS = -2.5 V • Very low level gate drive requirements allowing direct operation in 3V circuits (V GS(TH) < 1.
PAGE 2
Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = -250µA, VGS = 0V -20 - - V IDSS Zero Gate Voltage Drain Current VGS = −16V , VGS = 0V - - -3 µA IGSS Gate to Source Leakage Current VGS = ±12V , VGS = 0V - - ±10 µA V On Characteristics VGS(TH) rDS(ON) Gate to Source Threshold Voltage Drain to Source On Resistance VGS = VDS, ID = -250µA -0.65 -0.9 -1.5 ID = -0.5A, VGS = -4.5V - 580 780 ID = -0.
PAGE 3
FDG6318PZ Typical Characteristic TA = 25°C unless otherwise noted 0.6 1.2 -ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER 1.0 0.8 0.6 0.4 VGS = -4.5V 0.4 VGS = -2.5V 0.2 0.2 0 0 0 25 50 75 100 125 150 25 50 TA , AMBIENT TEMPERATURE (oC) 75 100 125 150 TA, CASE TEMPERATURE (oC) Figure 1. Normalized Power Dissipation vs Ambient Temperature Figure 2. Maximum Continuous Drain Current vs Case Temperature 2 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.
PAGE 4
FDG6318PZ Typical Characteristic (Continued) TA = 25°C unless otherwise noted 3 -ID, DRAIN CURRENT (A) -ID, DRAIN CURRENT (A) 10 100µs 1 1ms OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 10ms PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VDD = -10V TJ = 150oC 2 TJ = 25oC TJ = -55oC 1 SINGLE PULSE TJ = MAX RATED TA = 25oC 0.1 0.05 0 1 10 0 30 1 VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 5. Forward Bias Safe Operating Area 3 4 Figure 6. Transfer Characteristics 3 1.
PAGE 5
FDG6318PZ Typical Characteristic (Continued) TA = 25°C unless otherwise noted 200 ID = 250µA CISS = CGS + CGD 100 C, CAPACITANCE (pF) NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 1.10 1.05 1.00 COSS ≅ CDS + CGD CRSS = C GD 10 VGS = 0V, f = 1MHz 5 0.95 -80 -40 0 40 80 120 160 0.1 1 TJ , JUNCTION TEMPERATURE (oC) 10 20 -VDS , DRAIN TO SOURCE VOLTAGE (V) Figure 11. Normalized Drain to Source Breakdown Voltage vs Junction Temperature Figure 12.
PAGE 6
.SUBCKT FDG6318PZ 2 1 3 ; CA 12 8 0.6e-10 CB 15 14 1.1e-10 CIN 6 8 0.75e-10 rev January 2003 ESG 10 DBODY 5 7 DBODYMOD DBREAK 7 11 DBREAKMOD DPLCAP 10 6 DPLCAPMOD GATE 1 LDRAIN 2 5 1e-9 LGATE 1 9 0.47e-9 LSOURCE 3 7 0.47e-9 DRAIN 2 RLDRAIN RSLC1 51 + 5 ESLC 51 RSLC2 EBREAK 5 11 17 18 -23.
PAGE 7
REV January 2003 template fdg6318pz n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl = 7.7e-11, nl=1.277, rs = 1e-3, trs1 = 2.8e-1, trs2 = 3e-4, xti=0, cjo = 3.9e-11, ikf=0.5, tt = 33e-9, m = 0.50) dp..model dbreakmod = (rs = 5.3e-1, trs1 = 5.5e-3, trs2 = -9.0e-5) dp..model dplcapmod = (cjo = 0.5e-10, isl=10e-30, nl=10, m=0.55) m..model mmedmod = (type=_p, vto = -1.17, kp=0.6, is=1e-30, tox=1) m..model mstrongmod = (type=_p, vto = -1.45, kp = 1.5, is = 1e-30, tox = 1) m..
PAGE 8
th REV January 2003 FDG6318PZ_JA Junction Ambient Copper Area= 1sq.in CTHERM1 Junction c2 0.17e-4 CTHERM2 c2 c3 2.7e-4 CTHERM3 c3 c4 5.5e-4 CTHERM4 c4 c5 1.4e-3 CTHERM5 c5 c6 2.2e-3 CTHERM6 c6 c7 2.6e-3 CTHERM7 c7 c8 6.6e-3 CTHERM8 c8 Ambient 0.29 RTHERM1 Junction c2 11.2 RTHERM2 c2 c3 11.5 RTHERM3 c3 c4 12.5 RTHERM4 c4 c5 27 RTHERM5 c5 c6 81 RTHERM6 c6 c7 88 RTHERM7 c7 c8 92 RTHERM8 c8 Ambient 93 CTHERM1 RTHERM1 8 CTHERM2 RTHERM2 7 RTHERM3 CTHERM3 6 RTHERM4 rtherm.rtherm1 th c2 = 11.2 rtherm.
PAGE 9
TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ FACT™ ActiveArray™ FACT Quiet Series™ Bottomless™ FAST® CoolFET™ FASTr™ CROSSVOLT™ FRFET™ DOME™ GlobalOptoisolator™ EcoSPARK™ GTO™ E2CMOS™ HiSeC™ I2C™ EnSigna™ Across the board. Around the world.