Datasheet

November 1998
FDG6321C
Dual N & P Channel Digital FET
General Description Features
Absolute Maximum Ratings T
A
= 25
o
C unless otherwise noted
Symbol Parameter N-Channel P-Channel Units
V
DS
S
Drain-Source Voltage 25 -25 V
V
GSS
Gate-Source Voltage 8 -8 V
I
D
Drain Current - Continuous 0.5 -0.41 A
- Pulsed 1.5 -1.2
P
D
Maximum Power Dissipation (Note 1) 0.3 W
T
J
,T
STG
Operating and Storage Temperature Ranger -55 to 150 °C
ESD Electrostatic Discharge Rating MIL-STD-883D
Human Body Model (100pf / 1500 Ohm)
6 kV
THERMAL CHARACTERISTICS
R
θJA
Thermal Resistance, Junction-to-Ambient (Note 1) 415 °C/W
FDG6321C Rev. D
N-Ch 0.50 A, 25 V, R
DS(ON)
= 0.45 Ω @ V
GS
= 4.5V.
R
DS(ON)
= 0.60 Ω @ V
GS
= 2.7 V.
P-Ch -0.41 A, -25 V,R
DS(ON)
= 1.1 Ω @ V
GS
= -4.5V.
R
DS(ON)
= 1.5 Ω @ V
GS
= -2.7V.
Very small package outline SC70-6.
Very low level gate drive requirements allowing direct
operation in 3 V circuits(V
GS(th)
< 1.5 V).
Gate-Source Zener for ESD ruggedness
(>6kV Human Body Model).
These dual N & P-Channel logic level enhancement mode field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance.
This device has been designed especially for low voltage
applications as a replacement for bipolar digital transistors and
small signal MOSFETS. Since bias resistors are not required,
this dual digital FET can replace several different digital
transistors, with different bias resistor values.
SC70-6
SuperSOT
TM
-6
SOIC-14
SO-8
SOT-8
SOT-23
SC70-6
G1
D2
S1
D1
S2
G2
.21
5
3
2
4
1
6
© 1998 Fairchild Semiconductor Corporation