Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFDG8850NZ, MOSFET

April 2007

FDG8850NZ Dual N-Channel PowerTrench

MOSFET

FDG8850NZ Rev.B

www.fairchildsemi.com

FDG8850NZ

Dual N-Channel PowerTrench

MOSFET

30V,0.75A,0.4Ω

Features

 Max r

DS(on)

= 0.4Ω at V

= 4.5V, I

= 0.75A

 Max r

DS(on)

= 0.5Ω at V

= 2.7V, I

= 0.67A

 Very low level gate drive requirements allowing operation

in 3V circuits(V

GS(th)

<1.5V)

 Very small package outline SC70-6

 RoHS Compliant

General Description

This dual N-Channel logic level enhancement mode field effect

transistors are produced using Fairchild’s proprietary, high cell

density, DMOS technology. This very high density process is

especially tailored to minimize on-state resistance. This device

has been designed especially for low voltage applications as

a replacement for bipolar digital transistors and small signal

MOSFETs. Since bias resistors are not required, this dual digital

FET can replace several different digital transistors, with differ

ent bias resistor values.

MOSFET Maximum Ratings T

= 25°C unless otherwise noted

Thermal Characteristics

Package Marking and Ordering Information

Symbol Parameter Ratings Units

Drain to Source Voltage 30 V

Gate to Source Voltage ±12 V

Drain Current -Continuous 0.75

-Pulsed 2.2

Power Dissipation for Single Operation (Note 1a)

(Note 1b)

0.36

0.30

, T

STG

Operating and Storage Junction Temperature Range –55 to +150 °C

θJA

Thermal Resistance, Junction to Ambient Single operation (Note 1a) 350

°C/W

θJA

Thermal Resistance, Junction to Ambient Single operation (Note 1b) 415

Device Marking Device Reel Size Tape Width Quantity

.50 FDG8850NZ 7” 8mm 3000 units

Pin 1

SC70-6

Summary of content (5 pages)

PAGE 1
FDG8850NZ tm Dual N-Channel PowerTrench® MOSFET 30V,0.75A,0.4Ω Features General Description Max rDS(on) = 0.4Ω at VGS = 4.5V, ID = 0.75A This dual N-Channel logic level enhancement mode field effect transistors are produced using Fairchild’s proprietary, high cell Max rDS(on) = 0.5Ω at VGS = 2.7V, ID = 0.67A density, DMOS technology. This very high density process is Very low level gate drive requirements allowing operation especially tailored to minimize on-state resistance.
PAGE 2
Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = 250μA, VGS = 0V ΔBVDSS ΔTJ Breakdown Voltage Temperature Coefficient 30 V ID = 250μA, referenced to 25°C IDSS Zero Gate Voltage Drain Current VDS = 24V, VGS = 0V 1 μA IGSS Gate to Source Leakage Current VGS = ±12V, VDS= 0V ±10 μA 1.
PAGE 3
2.6 VGS = 4.5V VGS = 2.7V VGS = 2.0V 1.76 ID, DRAIN CURRENT (A) NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 2.20 1.32 VGS =1.8V 0.88 PULSE DURATION = 80μs DUTY CYCLE = 0.5%MAX 0.44 0.00 0.0 VGS = 1.5V 0.5 1.0 1.5 VDS, DRAIN TO SOURCE VOLTAGE (V) VGS = 1.8V 2.2 1.8 0.6 0.00 2.0 0.44 0.88 1.32 1.76 2.20 Figure 2. Normalized On-Resistance vs Drain Current and Gate Voltage 0.8 ID = 0.75A VGS = 4.5V rDS(on), DRAIN TO ID =0.38A 1.2 1.0 0.8 -25 0 25 50 75 100 125 TJ = 125oC 0.
PAGE 4
VGS, GATE TO SOURCE VOLTAGE(V) 5 200 ID = 0.22A Ciss 100 3 VDD = 5V 2 CAPACITANCE (pF) 4 VDD = 10V VDD = 15V Coss 10 1 f = 1MHz VGS = 0V 0 0.0 0.2 0.4 0.6 0.8 1.0 Qg, GATE CHARGE(nC) 1.2 1 0.1 1.4 1 Figure 8. Capacitance vs Drain to Source Voltage 50 4 r DS n) (o ED P(PK), PEAK TRANSIENT POWER (W) 1 T MI LI 100μs 1ms 10ms 0.1 SINGLE PULSE TJ = MAX RATED 100ms RθJA = 415OC/W 0.01 1s DC TA = 25OC 0.005 0.1 1 30 10 VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 7.
PAGE 5
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