FDH038AN08A1 N-Channel PowerTrench® MOSFET 75 V, 80 A, 3.8 mΩ Features Applications • R DS(ON) = 3.5 m Ω (Typ.), VGS = 10 V, ID = 80 A • Synchronous Rectification for ATX / Server / Telecom PSU • Qg(tot) = 125 nC (Typ.
Device Marking FDH038AN08A1 Device FDH038AN08A1 Package TO-247 Reel Size Tube Tape Width N/A Quantity 30 units Electrical Characteristics TC = 25°C unless otherwise noted Symbol Parameter Test Conditions Min Typ Max Unit V Off Characteristics BVDSS Drain to Source Breakdown Voltage IDSS Zero Gate Voltage Drain Current IGSS Gate to Source Leakage Current ID = 250µA, VGS = 0V 75 - - - - 1 - - 250 VGS = ±20V - - ±100 nA VGS = VDS, ID = 250µA 2 - 4 V ID = 40A, VGS = 6V V
280 1.0 240 ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER 1.2 0.8 0.6 0.4 0.2 CURRENT LIMITED BY PACKAGE 200 160 120 80 40 0 0 25 50 75 100 150 125 VGS = 10V 0 175 25 TC , CASE TEMPERATURE (oC) Figure 1. Normalized Power Dissipation vs Ambient Temperature 50 75 100 125 TC, CASE TEMPERATURE (oC) 175 Figure 2. Maximum Continuous Drain Current vs Case Temperature 2 RθJA=30oC/W DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.
2000 500 IAS, AVALANCHE CURRENT (A) 10µs 1000 ID, DRAIN CURRENT (A) 100µs 100 1ms 10ms 10 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 1 DC SINGLE PULSE TJ = MAX RATED TC = 25oC 0.1 0.1 10 STARTING TJ = 150oC 0.01 160 VGS = 10V 175oC 80 TJ = -55 oC TJ = 25oC 40 0 VGS = 7V 120 VGS = 6V VGS = 5V 80 40 TC = 25oC PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0 VGS , GATE TO SOURCE VOLTAGE (V) Figure 7. Transfer Characteristics 6 2.
1.4 1.2 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE VGS = VDS, ID = 250µA NORMALIZED GATE THRESHOLD VOLTAGE 1.2 1.0 0.8 0.6 0.4 1.1 1.0 0.9 0.2 -80 -40 0 40 80 120 TJ, JUNCTION TEMPERATURE (o C) 160 -80 200 Figure 11. Normalized Gate Threshold Voltage vs Junction Temperature 20000 10 VGS , GATE TO SOURCE VOLTAGE (V) COSS ≅ CDS + CGD 1000 CRSS = CGD VGS = 0V, f = 1MHz 100 0.
VDS BVDSS tP L VARY tP TO OBTAIN REQUIRED PEAK IAS + RG - VGS VDS IAS VDD VDD DUT tP 0V IAS 0 0.01Ω tAV Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms VDS VDD Qg(TOT) VDS L VGS + - VGS VGS = 10V Qgs2 VDD DUT VGS = 2V Ig(REF) 0 Qg(TH) Qgs Qgd Ig(REF) 0 Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms VDS tON tOFF td(ON) td(OFF) RL tr VDS 90% - VDD 10% 0 10% DUT 90% VGS VGS 0 Figure 19.
.SUBCKT FDH038AN08A1 2 1 3 ; CA 12 8 1.0e-9 Cb 15 14 3.1e-9 Cin 6 8 8.22e-9 rev January 2003 DPLCAP 10 RSLC2 ESG + GATE 1 Lgate 1 9 4.81e-9 Ldrain 2 5 1.0e-9 Lsource 3 7 4.63e-9 LGATE RLGATE DBREAK ESLC 11 + 17 EBREAK 18 - 50 RDRAIN 6 8 EVTEMP RGATE + 18 22 9 20 EVTHRES + 19 8 6 21 16 DBODY MWEAK MMED MSTRO CIN LSOURCE 8 7 RSOURCE RLgate 1 9 48.1 RLdrain 2 5 10 RLsource 3 7 46.3 Mmed 16 6 8 8 MmedMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD 5 51 - Ebreak 11 7 17 18 84.
REV January 2003 template FDH038AN08A1 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl=2.4e-11,nl=1.02,rs=1.65e-3,trs1=3.2e-3,trs2=2.0e-7,cjo=6.0e-9,m=5.6e-1,tt=2.38e-8,xti=3.9) dp..model dbreakmod = (rs=1.5e-1,trs1=1.0e-3,trs2=-8.9e-6) dp..model dplcapmod = (cjo=1.5e-9,isl=10e-30,nl=10,m=0.47) m..model mmedmod = (type=_n,vto=3.2,kp=1.5,is=1e-30, tox=1) m..model mstrongmod = (type=_n,vto=3.95,kp=235,is=1.0e-30, tox=1) m..model mweakmod = (type=_n,vto=2.73,kp=0.02,is=1.0e-30, tox=1,rs=0.
th REV 23 January 2003 JUNCTION FDH038AN08A1T CTHERM1 TH 6 5.5e-3 CTHERM2 6 5 6.0e-3 CTHERM3 5 4 7.4e-3 CTHERM4 4 3 7.65e-3 CTHERM5 3 2 5.85e-2 CTHERM6 2 TL 6.0e-1 RTHERM1 RTHERM1 TH 6 9.0e-3 RTHERM2 6 5 2.08e-2 RTHERM3 5 4 2.28e-2 RTHERM4 4 3 7.0e-2 RTHERM5 3 2 7.5e-2 RTHERM6 2 TL 8.5e-2 RTHERM2 CTHERM1 6 CTHERM2 5 SABER Thermal Model SABER thermal model FDH038AN08A1T template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 =5.5e-3 ctherm.ctherm2 6 5 =6.0e-3 ctherm.ctherm3 5 4 =7.
FDH038AN08A1 — N-Channel PowerTrench® MOSFET Mechanical Dimensions TO-247 3L Figure 21. TO-247, Molded, 3 Lead, Jedec Variation AB Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
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