Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFDMA1024NZ, MOSFET

FDMA1024NZ Rev.B5

www.fairchildsemi.com

FDMA1024NZ Dual N-Channel Power Trench

MOSFET

S1 G1 D2

MicroFET 2x2

D1 G2

PIN 1

D1 D2

FDMA1024NZ

Dual N-Channel PowerTrench

MOSFET

20 V, 5.0 A, 54 mΩ

Features

 Max r

DS(on)

= 54 mΩ at V

= 4.5 V, I

= 5.0 A

 Max r

DS(on)

= 66 mΩ at V

= 2.5 V, I

= 4.2 A

 Max r

DS(on)

= 82 mΩ at V

= 1.8 V, I

= 2.3 A

 Max r

DS(on)

= 114 mΩ at V

= 1.5 V, I

= 2.0 A

 HBM ESD protection level = 1.6 kV (Note 3)

 Low profile - 0.8 mm maximum - in the new package

MicroFET 2x2 mm

 RoHS Compliant

General Description

This device is designed specifically as a single package solution

for dual switching requirements in cellular handset and other

ultra-portable applications. It features two independent

N-Channel MOSFETs with low on-state resistance for minimum

conduction losses.

The MicroFET 2X2 package offers exceptional thermal

performance for its physical size and is well suited to linear mo de

applications.

Applications

 Baseband Switch

 Loadswitch

 DC-DC Conversion

MOSFET Maximum Ratings

= 25 °C unless otherwise noted

Thermal Characteristics

Package Marking and Ordering Information

Symbol Parameter Ratings Units

Drain to Source Voltage 20 V

Gate to Source Voltage ±8 V

Drain Current -Continuous (Note 1a) 5.0

-Pulsed 6.0

Power Dissipation (Note 1a) 1.4

Power Dissipation (Note 1b) 0.7

, T

STG

Operating and Storage Junction Temperature Range –55 to +150 °C

θJA

Thermal Resistance, Junction to Ambient (Note 1a) 86 (Single Operation)

°C/W

θJA

Thermal Resistance, Junction to Ambient (Note 1b) 173 (Single Operation)

θJA

Thermal Resistance, Junction to Ambient (Note 1c) 69 (Dual Operation)

θJA

Thermal Resistance, Junction to Ambient (Note 1d) 151 (Dual Operation)

Device Marking Device Package Reel Size Tape Width Quantity

024 FDMA1024NZ MicroFET 2X2 7 ” 8 mm 3000 units



Free from halogenated compounds and ant imony

oxides

July 2014

Summary of content (8 pages)

PAGE 1
FDMA1024NZ Dual N-Channel PowerTrench® MOSFET 20 V, 5.0 A, 54 mΩ Features General Description Max rDS(on) = 54 mΩ at VGS = 4.5 V, ID = 5.0 A This device is designed specifically as a single package solution for dual switching requirements in cellular handset and other ultra-portable applications. It features two independent N-Channel MOSFETs with low on-state resistance for minimum conduction losses. Max rDS(on) = 66 mΩ at VGS = 2.5 V, ID = 4.2 A Max rDS(on) = 82 mΩ at VGS = 1.8 V, ID = 2.
PAGE 2
Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ∆BVDSS ∆TJ Breakdown Voltage Temperature Coefficient IGSS Gate to Source Leakage Current IDSS Zero Gate Voltage Drain Current ID = 250 µA, VGS = 0 V 20 ID = 250 µA, referenced to 25 °C V 19 VDS = 16 V, VGS = 0 V VGS = ±8 V, VDS = 0 V mV/°C 1 µA ±10 µA 1.
PAGE 3
1. RθJA is determined with the device mounted on a 1 in 2 oz. copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθJA is determined by the user's board design. (a) RθJA = 86 °C/W when mounted on a 1 in2 pad of 2 oz copper, 1.5 " x 1.5 " x 0.062 " thick PCB. For single operation. (b) RθJA = 173 °C/W when mounted on a minimum pad of 2 oz copper. For single operation. (c) RθJA = 69 oC/W when mounted on a 1 in2 pad of 2 oz copper, 1.5 ” x 1.5 ” x 0.062 ” thick PCB.
PAGE 4
6 VGS = 1.5 V 5 ID, DRAIN CURRENT (A) NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 3.0 VGS = 4.5 V 4 VGS = 3.5 V VGS = 2.5 V VGS = 1.8 V 3 2 1 PULSE DURATION = 80 µs DUTY CYCLE = 0.5% MAX 0 0.0 0.2 0.4 0.6 0.8 0.5 2 3 200 4 5 SOURCE ON-RESISTANCE (mΩ) rDS(on), DRAIN TO 0.8 120 80 TJ = 125 oC 40 TJ = 25 oC 0 1.0 -25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (oC) ID = 2.5 A 1.5 2.0 2.5 3.0 3.5 4.0 Figure 4.
PAGE 5
VGS, GATE TO SOURCE VOLTAGE (V) 5 1000 ID = 5 A Ciss 3 VDD = 10 V VDD = 8 V 2 CAPACITANCE (pF) 4 VDD = 12 V 1 0 0 1 2 3 4 5 100 Coss 10 0.1 6 1 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) Figure 7. Gate Charge Characteristics 20 10 -2 100 us VGS = 0 V -3 10 ID, DRAIN CURRENT (A) Ig, GATE LEAKAGE CURRENT (A) 10 Figure 8.Capacitance vs Drain to Source Voltage 10 -4 10 TJ = 125 oC -5 10 -6 10 TJ = 25 oC 0 3 6 9 12 0.
PAGE 6
2 NORMALIZED THERMAL IMPEDANCE, ZθJA 1 0.1 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA SINGLE PULSE o RθJA = 173 C/W 0.01 -3 10 -2 10 -1 10 1 10 100 1000 t, RECTANGULAR PULSE DURATION (sec) Figure 12. Junction to Ambient Transient Thermal Response Curve ©2010 Fairchild Semiconductor Corporation FDMA1024NZ Rev.B5 6 www.fairchildsemi.
PAGE 7
FDMA1024NZ Dual N-Channel Power Trench® MOSFET Dimensional Outline and Pad Layout Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
PAGE 8
tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.