Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFDMA1029PZ, MOSFET

2009 Fairchild Semiconductor Corporation

FDMA1029PZ

Dual P-Channel PowerTrench



MOSFET

General Description

This device is designed specifically as a single package

solution for the battery charge switch in cellular handset

and other ultra-portable applications. It features two

independent P-Channel MOSFETs with low on-state

resistance for minimum conduction losses. When

connected in the typical common source configuration,

bi-directional current flow is possible.

The MicroFET 2x2 package offers exceptional thermal

performance for its physical size and is well suited to

linear mode applications.

Features

x –3.1 A, –20V. R

DS(ON)

= 95 m: @ V

= –4.5V

DS(ON)

= 141 m: @ V

= –2.5V

x Low profile – 0.8 mm maximum – in the new package

MicroFET 2x2 mm

x RoHS Compliant

Absolute Maximum Ratings

=25

C unless otherwise noted

Symbol Parameter Ratings Units

Drain-Source Voltage –20 V

Gate-Source Voltage

r12

Drain Current – Continuous

(Note 1a)

–3.1

– Pulsed –6

Power Dissipation for Single Operation

(Note 1a)

1.4

(Note 1b)

0.7

, T

STG

Operating and Storage Junction Temperature Range –55 to +150

Thermal Characteristics

TJA

Thermal Resistance, Junction-to-Ambient

(Note 1a)

86 (Single Operation)

TJA

Thermal Resistance, Junction-to-Ambient

(Note 1b)

173 (Single Operation)

TJA

Thermal Resistance, Junction-to-Ambient

(Note 1c)

69 (Dual Operation)

TJA

Thermal Resistance, Junction-to-Ambient

(Note 1d)

151 (Dual Operation)

qC/W

Package Marking and Ordering Information

Device Marking Device Reel Size Tape width Quantity

029 FDMA1029PZ 7’’ 8mm 3000 units

FDMA1029PZ Dual P-Channel PowerTrench



MOSFET

MicroFET 2x2

PIN 1

S1 G1 D2

D1 G2 S2

D1 D2

x HBM ESD protection level > 2.5kV (Note 3)



Free from halogenated compounds and antimony

oxides



FDMA1029PZ Rev.B4(W)

July 2014

Summary of content (7 pages)

PAGE 1
FDMA1029PZ Dual P-Channel PowerTrench MOSFET General Description Features This device is designed specifically as a single package x –3.1 A, –20V. RDS(ON) = 95 m: @ VGS = –4.5V solution for the battery charge switch in cellular handset RDS(ON) = 141 m: @ VGS = –2.5V x Low profile – 0.8 mm maximum – in the new package and other ultra-portable applications. It features two independent P-Channel MOSFETs with low on-state resistance for minimum conduction losses.
PAGE 2
Symbol Parameter TA = 25°C unless otherwise noted Test Conditions Min Typ Max Units Off Characteristics BVDSS 'BVDSS 'TJ IDSS IGSS Drain–Source Breakdown Voltage Breakdown Voltage Temperature Coefficient ID = –250 PA VGS = 0 V, ID = –250 PA, Referenced to 25qC –20 V mV/qC –12 Zero Gate Voltage Drain Current VDS = –16 V, VGS = 0 V –1 PA Gate–Body Leakage VGS = ± 12 V, VDS = 0 V ±10 PA On Characteristics (Note 2) VGS(th) 'VGS(th) 'TJ RDS(on) Gate Threshold Voltage Gate Threshold
PAGE 3
Notes: 1. RTJA is determined with the device mounted on a 1 in2 oz. copper pad on a 1.5 x 1.5 in. board of FR-4 material. RTJC is guaranteed by design while RTJA is determined by the user's board design. (a) RTJA = 86 °C/W when mounted on a 1 in2 pad of 2 oz copper, 1.5 " x 1.5 " x 0.062 " thick PCB. For single operation. (b) RTJA = 173 °C/W when mounted on a minimum pad of 2 oz copper. For single operation. (c) RTJA = 69 oC/W when mounted on a 1 in2 pad of 2 oz copper, 1.5 ” x 1.5 ” x 0.062 ” thick PCB.
PAGE 4
6 2.6 VGS = 4 5V 3.5V RDS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE -ID, DRAIN CURRENT (A) 5 2.5V 2.0V 3.0V 4 3 2 1 1.5V 0 1.8 -2.5V 1.4 -3.0V -3.5V 1 0.4 0.8 1.2 1.6 -VDS, DRAIN-SOURCE VOLTAGE (V) 2 0 Figure 1. On-Region Characteristics. -4.5V 1 2 3 4 -ID, DRAIN CURRENT (A) 5 6 Figure 2. On-Resistance Variation with Drain Current and Gate Voltage. 0.2 1.5 1.4 RDS(ON), ON-RESISTANCE (OHM) ID = -3.1A VGS = -4.5V 1.3 1.2 1.1 1 0.9 0.8 0.7 ID = -1.55A 0.16 0.12 o TA = 125 C 0.
PAGE 5
1000 f = 1MHz VGS = 0 V ID = -3.1A 800 8 VDS = -5V CAPACITANCE (pF) -VGS, GATE-SOURCE VOLTAGE (V) 10 -15V 6 -10V 4 600 Ciss 400 Coss 2 200 0 0 Crss 0 2 4 6 8 10 Qg, GATE CHARGE (nC) 12 14 0 Figure 7. Gate Charge Characteristics. 4 8 12 16 -VDS, DRAIN TO SOURCE VOLTAGE (V) 20 Figure 8. Capacitance Characteristics. 100 RDS(ON) LIMIT P(pk), PEAK TRANSIENT POWER (W) 10 100us 1ms 10ms 100ms 1 10s 1s DC VGS = -4.5V SINGLE PULSE o RTJA = 173 C/W 0.1 TA = 25oC 0.01 0.
PAGE 6
FDMA1029PZ Dual P-Channel PowerTrench MOSFET Dimensional Outline and Pad Layout Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
PAGE 7
tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.