Datasheet

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FDMA3027PZ Rev.C1

www.fairchildsemi.com

FDMA3027PZ Dual P-Channel PowerTrench

MOSFET

FDMA3027PZ

Dual P-Channel PowerTrench

MOSFET

-30 V, -3.3 A, 87 mΩ

Features

 Max r

DS(on)

= 87 mΩ at V

= -10 V, I

= -3.3 A

 Max r

DS(on)

= 152 mΩ at V

= -4.5 V, I

= -2.3 A

 HBM ESD protection level > 2 KV typical (Note 3)

 Low profile - 0.8 mm maximum - in the new package

MicroFET 2x2 mm

 RoHS Compliant

General Description

This device is designed specifically as a single package solution

for dual switching requirements such as gate driver for larger

Mosfets. It features two independent P-Channel MOSFETs with

low on-state resistance for minimum conduction losses. The

MicroFET 2x2 package offers exceptional thermal performance

for its physical size and is well suited to linear mode applications.

G-S zener has been added to enhance ESD voltage level.

Applications

 Load Switch

 Discrete Gate Driver

S1 G1 D2

MicroFET 2x2

D1 G2

PIN 1

D1 D2

Top Bottom

MOSFET Maximum Ratings

= 25 °C unless otherwise noted

Thermal Characteristics

Package Marking and Ordering Information

Symbol Parameter Ratings Units

Drain to Source Voltage -30 V

Gate to Source Voltage ±25 V

Drain Current -Continuous (Note 1a) -3.3

-Pulsed -15

Power Dissipation (Note 1a) 1.4

Power Dissipation (Note 1b) 0.7

, T

STG

Operating and Storage Junction Temperature Range -55 to +150 °C

θJA

Thermal Resistance for Single Operation, Junction to Ambient (Note 1a) 86

°C/W

Thermal Resistance for Single Operation, Junction to Ambient (Note 1b) 173

Thermal Resistance for Dual Operation, Junction to Ambient (Note 1c) 69

Thermal Resistance for Dual Operation, Junction to Ambient (Note 1d) 151

Thermal Resistance for Single Operation, Junction to Ambient (Note 1e) 160

Thermal Resistance for Dual Operation, Junction to Ambient (Note 1f) 133

Device Marking Device Package Reel Size Tape Width Quantity

327 FDMA3027PZ MicroFET 2X2 7 ’’ 8 mm 3000 units

July 2014

Summary of content (8 pages)

PAGE 1
FDMA3027PZ Dual P-Channel PowerTrench® MOSFET -30 V, -3.3 A, 87 mΩ Features General Description This device is designed specifically as a single package solution for dual switching requirements such as gate driver for larger Mosfets. It features two independent P-Channel MOSFETs with low on-state resistance for minimum conduction losses. The MicroFET 2x2 package offers exceptional thermal performance for its physical size and is well suited to linear mode applications.
PAGE 2
Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = -250 μA, VGS = 0 V ΔBVDSS ΔTJ Breakdown Voltage Temperature Coefficient ID = -250 μA, referenced to 25 °C IDSS Zero Gate Voltage Drain Current VDS = -24 V, VGS = 0 V -1 μA IGSS Gate to Source Leakage Current VGS = ±25 V, VDS = 0 V ±10 μA -3 V -30 V -22 mV/°C On Characteristics VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = -250 μA ΔVGS(th) ΔTJ Gate to
PAGE 3
Notes: 1. RθJA is determined with the device mounted on a 1 in2 oz. copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθJA is determined by the user's board design. (a) RθJA = 86 °C/W when mounted on a 1 in2 pad of 2 oz copper, 1.5 " x 1.5 " x 0.062 " thick PCB. For single operation. (b) RθJA = 173 °C/W when mounted on a minimum pad of 2 oz copper. For single operation. (c) RθJA (d) RθJA (e) RθJA (f) RθJA = 69 oC/W when mounted on a 1 in2 pad of 2 oz copper, 1.
PAGE 4
15 -ID, DRAIN CURRENT (A) NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 5 VGS = -5 V VGS = -10 V 12 VGS = -4.5 V 9 VGS = -4 V 6 VGS = -3.5 V 3 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 0 0 1 2 3 4 5 VGS = -3.5 V 4 VGS = -4 V 3 VGS = -4.5 V 2 VGS = -5 V 1 0 0 3 -VDS, DRAIN TO SOURCE VOLTAGE (V) rDS(on), DRAIN TO 1.2 1.1 1.0 0.9 0.8 SOURCE ON-RESISTANCE (mΩ) NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 1.
PAGE 5
1000 -VGS, GATE TO SOURCE VOLTAGE (V) 10 VDD = -15 V ID = -3.3 A Ciss CAPACITANCE (pF) 8 VDD = -20 V VDD = -10 V 6 4 Coss 100 Crss 2 f = 1 MHz VGS = 0 V 0 0 2 4 6 10 0.1 8 Figure 7. Gate Charge Characteristics -1 30 20 VDS = 0 V -2 10 10 -ID, DRAIN CURRENT (A) -Ig, GATE LEAKAGE CURRENT (A) 10 Figure 8. Capacitance vs Drain to Source Voltage 10 -3 10 -4 10 -5 10 TJ = 125 oC -6 10 -7 10 TJ = 25 oC 1 1 ms THIS AREA IS LIMITED BY rDS(on) 0.
PAGE 6
2 DUTY CYCLE-DESCENDING ORDER NORMALIZED THERMAL IMPEDANCE, ZθJA 1 D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 0.1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA SINGLE PULSE o RθJA = 173 C/W 0.02 -3 10 -2 10 -1 10 1 10 100 1000 t, RECTANGULAR PULSE DURATION (sec) Figure 12. Junction-to-Ambient Transient Thermal Response Curve ©2012 Fairchild Semiconductor Corporation FDMA3027PZ Rev.C1 6 www.fairchildsemi.
PAGE 7
FDMA3027PZ Dual P-Channel PowerTrench® MOSFET Dimensional Outline and Pad Layout Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
PAGE 8
tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.