Datasheet

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FDMA510PZ Single P-Channel PowerTrench

MOSFET

FDMA510PZ Rev.B3

www.fairchildsemi.com

FDMA510PZ

Single P-Channel PowerTrench

MOSFET

–20V, –7.8A, 30m:

Features

 Max r

DS(on)

= 30m: at V

= –4.5V, I

= –7.8A

 Max r

DS(on)

= 37m: at V

= –2.5V, I

= –6.6A

 Max r

DS(on)

= 50m: at V

= –1.8V, I

= –5.5A

 Max r

DS(on)

= 90m: at V

= –1.5V, I

= –2.0A

 Low profile - 0.8mm maximum - in the new package MicroFET

2X2 mm

 HBM ESD protection level > 3KV typical (Note 3)

 Free from halogenated compounds and antimony oxides

General Description

This device is designed specifically for battery charge or load

switching in cellular handset and other ultraportable applications.

It features a MOSFET with low on-state resistance.

The MicroFET 2X2 package offers exceptional thermal

perfo

rmance for

its physical size and is well suited to linear mode

applications.

MOSFET Maximum Ratings

= 25°C unless otherwise noted

Thermal Characteristics

Package Marking and Ordering Information

Symbol Parameter Ratings Units

Drain to Source Voltage –20 V

Gate to Source Voltage ±8 V

Drain Current -Continuous (Note 1a) –7.8

-Pulsed –24

Power Dissipation (Note 1a) 2.4

Power Dissipation (Note 1b) 0.9

, T

STG

Operating and Storage Junction Temperature Range –55 to +150 °C

TJA

Thermal Resistance, Junction to Ambient (Note 1a) 52

°C/W

TJA

Thermal Resistance, Junction to Ambient (Note 1b) 145

Device Marking Device Package Reel Size Tape Width Quantity

510 FDMA510PZ MicroFET 2X2 7’’ 8mm 3000units

Bottom Drain Contact

Pin 1

Drain

Source

MicroFET 2X2 (Bottom View)

 RoHS Compliant

June 2014

Summary of content (7 pages)

PAGE 1
FDMA510PZ Single P-Channel PowerTrench® MOSFET –20V, –7.8A, 30m: Features General Description Max rDS(on) = 30m: at VGS = –4.5V, ID = –7.8A This device is designed specifically for battery charge or load switching in cellular handset and other ultraportable applications. It features a MOSFET with low on-state resistance. Max rDS(on) = 37m: at VGS = –2.5V, ID = –6.6A Max rDS(on) = 50m: at VGS = –1.8V, ID = –5.5A Max rDS(on) = 90m: at VGS = –1.5V, ID = –2.0A Low profile - 0.
PAGE 2
Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = –250PA, VGS = 0V 'BVDSS 'TJ Breakdown Voltage Temperature Coefficient –20 V ID = –250PA, referenced to 25°C IDSS Zero Gate Voltage Drain Current VDS = –16V, VGS = 0V –1 PA IGSS Gate to Source Leakage Current VGS = ±8V, VDS = 0V ±10 PA –1.
PAGE 3
24 20 -ID, DRAIN CURRENT (A) NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 2.5 VGS = -4.5V VGS = -1.8V VGS = -2.5V 16 VGS = -2V 12 VGS = -1.5V 8 4 PULSE DURATION = 80Ps DUTY CYCLE = 0.5%MAX 0 0 1 2 3 4 VGS = -1.5V VGS = -1.8V 2.0 VGS = -2V 1.5 VGS = -2.5V 1.0 0.5 0 4 -VDS, DRAIN TO SOURCE VOLTAGE (V) 12 16 20 24 Figure 2. Normalized On-Resistance vs Drain Current and Gate Voltage 1.6 1.4 1.2 1.0 0.8 0.6 -75 -50 -25 0 25 50 75 SOURCE ON-RESISTANCE (m:) 200 ID = -7.8A VGS = -4.
PAGE 4
3000 ID = -7.8A Ciss CAPACITANCE (pF) -VGS, GATE TO SOURCE VOLTAGE(V) 4.5 3.0 VDD = -3V VDD = -5V VDD = -7V 1.5 5 10 15 Coss f = 1MHz VGS = 0V 20 Figure 7. Gate Charge Characteristics 10 20 Figure 8. Capacitance vs Drain to Source Voltage 30 -1 10 -2 10 VDS = 0V 10 -ID, DRAIN CURRENT (A) -Ig, GATE LEAKAGE CURRENT(A) 1 -VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE(nC) -3 10 -4 10 TJ = 125oC -5 10 -6 10 -7 10 -8 100us 1ms 1 10ms THIS AREA IS LIMITED BY rDS(on) 0.
PAGE 5
NORMALIZED THERMAL IMPEDANCE, ZTJA 2 1 0.1 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 0.01 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZTJA x RTJA + TA SINGLE PULSE o RTJA = 145 C/W 1E-3 -4 10 -3 10 -2 10 -1 0 10 10 1 10 2 10 3 10 t, RECTANGULAR PULSE DURATION (s) Figure 12. Transient Thermal Response Curve ©2009 Fairchild Semiconductor Corporation FDMA510PZ Rev.B3 5 www.fairchildsemi.
PAGE 6
FDMA510PZ Single P-Channel PowerTrench® MOSFET Dimensional Outline and Pad Layout Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
PAGE 7
tm m *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.