Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFDMA6023PZT, MOSFET

June 2009

FDMA6023PZT Rev.B1

www.fairchildsemi.com

FDMA6023PZT Dual P-Channel PowerTrench

MOSFET

FDMA6023PZT

Dual P-Channel PowerTrench

MOSFET

-20 V, -3.6 A, 60 mΩ

Features

 Max r

DS(on)

= 60 mΩ at V

= -4.5 V, I

= -3.6 A

 Max r

DS(on)

= 80 mΩ at V

= -2.5 V, I

= -3.0 A

 Max r

DS(on)

= 110 mΩ at V

= -1.8 V, I

= -2.0 A

 Max r

DS(on)

= 170 mΩ at V

= -1.5 V, I

= -1.0 A

 Low Profile-0.55 mm maximum - in the new package

MicroFET 2x2 mm Thin

 HBM ESD protection level > 2.4 kV typical (Note 3)

 RoHS Compliant

 Free from halogenated compounds and antimony oxides

General Description

This device is designed specifically as a single package solution

for the battery charge switch in cellular handset and other

ultraportable applications. It features two independent

P-Channel MOSFETs with low on-state resistance for minimum

conduction losses. When connected in the typical common

source configuration, bi-directional current flow is possible.

The MicroFET 2X2 Thin package offers exceptional thermal

performance for it’s physical size and is well suited to linear

mode applications.

Applications

 Battery protection

 Battery management

 Load switch

MOSFET Maximum Ratings T

= 25 °C unless otherwise noted

Thermal Characteristics

Package Marking and Ordering Information

Symbol Parameter Ratings Units

Drain to Source Voltage -20 V

Gate to Source Voltage ±8 V

-Continuous T

= 25 °C (Note 1a) -3.6

-Pulsed -15

Power Dissipation T

= 25 °C (Note 1a) 1.4

Power Dissipation T

= 25 °C (Note 1b) 0.7

, T

STG

Operating and Storage Junction Temperature Range -55 to +150 °C

θJA

Thermal Resistance for Single Operation, Junction to Ambient (Note 1a) 86

°C/W

θJA

Thermal Resistance for Single Operation, Junction to Ambient (Note 1b) 173

θJA

Thermal Resistance for Dual Operation, Junction to Ambient (Note 1c) 69

θJA

Thermal Resistance for Dual Operation, Junction to Ambient (Note 1d) 151

Device Marking Device Package Reel Size Tape Width Quantity

623 FDMA6023PZT MicroFET 2X2 Thin 7 ’’ 8mm 3000 units

S1 G1 D2

MicroFET 2x2

D1 G2

Pin 1

D1 D2

Summary of content (7 pages)

PAGE 1
FDMA6023PZT Dual P-Channel PowerTrench® MOSFET -20 V, -3.6 A, 60 mΩ Features General Description Max rDS(on) = 60 mΩ at VGS = -4.5 V, ID = -3.6 A This device is designed specifically as a single package solution for the battery charge switch in cellular handset and other ultraportable applications. It features two independent P-Channel MOSFETs with low on-state resistance for minimum conduction losses. When connected in the typical common source configuration, bi-directional current flow is possible.
PAGE 2
Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = -250 µA, VGS = 0 V ∆BVDSS ∆TJ Breakdown Voltage Temperature Coefficient ID = -250 µA, referenced to 25 °C IDSS Zero Gate Voltage Drain Current VDS = -16 V, VGS = 0 V -1 µA IGSS Gate to Source Leakage Current VGS = ±8 V, VDS = 0 V ±10 µA -1.
PAGE 3
Notes: 1. RθJA is determined with the device mounted on a 1 in2 oz. copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθJA is determined by the user's board design. (a) RθJA= 86 °C/W when mounted on a 1 in2 pad of 2 oz copper, 1.5 " x 1.5 " x 0.062 " thick PCB. For single operation. (b) RθJA = 173 °C/W when mounted on a minimum pad of 2 oz copper. For single operation. (c) RθJA = 69 °C/Wwhen mounted on a 1 in2 pad of 2 oz copper, 1.5 " x 1.5 " x 0.062 " thick PCB.
PAGE 4
15 3.0 VGS = -2.0V NORMALIZED DRAIN TO SOURCE ON-RESISTANCE -ID, DRAIN CURRENT (A) VGS = -4.5V VGS = -3.0V 12 VGS = -2.5V VGS = -1.8V 9 VGS = -1.5V 6 3 PULSE DURATION = 300 µs DUTY CYCLE = 2.0% MAX 0 0.0 0.5 1.0 1.5 PULSE DURATION = 300 µs DUTY CYCLE = 2.0% MAX 2.5 VGS = -1.5V 2.0 VGS = -2.0V VGS = -1.8V 1.5 1.0 2.0 0 3 6 -VDS, DRAIN TO SOURCE VOLTAGE (V) 12 15 Figure 2. Normalized On-Resistance vs Drain Current and Gate Voltage 200 ID = -3.6A VGS = -4.5V rDS(on), DRAIN TO 1.4 1.
PAGE 5
2000 ID = -3.6A 1000 VDD = -5V 3.0 VDD = -10V VDD = -15V 1.5 Coss 100 4 8 12 16 1 10 20 -VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE(nC) Figure 7. Gate Charge Characteristics Figure 8. Capacitance vs Drain to Source Voltage 20 100 1 P(PK), PEAK TRANSIENT POWER (W) 10 -ID, DRAIN CURRENT (A) Crss f = 1MHz VGS = 0V 50 0.1 0.0 0 Ciss CAPACITANCE (pF) -VGS, GATE TO SOURCE VOLTAGE(V) 4.5 1 ms THIS AREA IS LIMITED BY rDS(on) 10 ms SINGLE PULSE TJ = MAX RATED 1s 10 s 0.
PAGE 6
FDMA6023PZT Dual P-Channel PowerTrench® MOSFET Dimensional Outline and Pad Layout ©2009 Fairchild Semiconductor Corporation FDMA6023PZT Rev.B1 6 www.fairchildsemi.
PAGE 7
tm tm tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.