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FDMA8878 Rev.C2

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FDMA8878 Single N-Channel Power Trench

MOSFET

May 2014

FDMA8878

Single N-Channel Power Trench

MOSFET

30 V, 9.0 A, 16 mΩ

Features

 Max r

DS(on)

= 16 mΩ at V

= 10 V, I

= 9.0 A

 Max r

DS(on)

= 19 mΩ at V

= 4.5 V, I

= 8.5 A

 High performance trench technology for extr

emely low r

DS(on)

 Fast switching speed

 RoHS Compliant

General Description

This N-Channel MOSFET is produced using Fairchild

Semiconductor‘s advanced Power Trench

process that has

been optimized for r

DS(on)

, switching performance.

Application

 DC/DC Buck Converters

 Load Switch in NB

 Notebook Battery Power Management

Pin 1

Drain

Source

MicroFET 2X2 (Bottom View)

Bottom Drain Contact

MOSFET Maximum Ratings T

= 25 °C unless otherwise noted

Thermal Characteristics

Package Marking and Ordering Information

Symbol Parameter Ratings Units

Drain to Source Voltage 30 V

Gate to Source Voltage (Note 3) ±20 V

Drain Current -Continuous (Package Limited) T

= 25 °C 10

A -Continuous T

= 25 °C (Note 1a) 9.0

-Pulse

Power Dissipation T

= 25 °C (Note 1a) 2.4

Power Dissipation T

= 25 °C (Note 1b) 0.9

, T

STG

Operating and Storage Junction Temperature Range -55 to +150 °C

θJA

Thermal Resistance, Junction to Ambient (Note 1a) 52

°C/W

Thermal Resistance, Junction to Ambient (Note 1b) 145R

θJA

Device Marking Device Package Reel Size Tape Width Quantity

878 FDMA8878 MicroFET 2x2 7 ’’ 8 mm 3000 units

Summary of content (6 pages)

PAGE 1
FDMA8878 Single N-Channel Power Trench® MOSFET 30 V, 9.0 A, 16 mΩ Features General Description Max rDS(on) = 16 mΩ at VGS = 10 V, ID = 9.0 A This N-Channel MOSFET is produced using Fairchild Semiconductor‘s advanced Power Trench® process that has been optimized for rDS(on), switching performance. Max rDS(on) = 19 mΩ at VGS = 4.5 V, ID = 8.
PAGE 2
Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V ΔBVDSS ΔTJ Breakdown Voltage Temperature Coefficient ID = 250 μA, referenced to 25 °C IDSS Zero Gate Voltage Drain Current VDS = 24 V, VGS = 0 V IGSS Gate to Source Leakage Current, Forward VGS = 20 V, VDS = 0 V 30 V 26 mV/°C 1 μA 100 nA 3.
PAGE 3
NORMALIZED DRAIN TO SOURCE ON-RESISTANCE ID, DRAIN CURRENT (A) 40 VGS = 10 V VGS = 4.5 V 32 VGS = 4 V VGS = 3.5 V 24 PULSE DURATION = 80μs DUTY CYCLE = 0.5%MAX 16 VGS = 3 V 8 0 0 1 2 3 VDS, DRAIN TO SOURCE VOLTAGE (V) 4 VGS = 3 V 5 VGS = 3.5 V 4 PULSE DURATION = 80μs DUTY CYCLE = 0.5%MAX 3 VGS = 4 V 2 1 0 VGS = 4.5 V VGS = 10 V 0 16 24 60 rDS(on), DRAIN TO 1.3 1.2 1.1 1.0 0.9 0.8 0.7 -75 -50 -25 0 25 50 75 SOURCE ON-RESISTANCE (mΩ) ID = 9 A VGS = 10 V 1.4 32 40 Figure 2.
PAGE 4
VDD = 10 V ID = 9 A Ciss 8 VDD = 15 V CAPACITANCE (pF) VGS, GATE TO SOURCE VOLTAGE (V) 1000 10 6 VDD = 20 V 4 Coss 100 2 Crss f = 1 MHz VGS = 0 V 0 0 2 4 6 8 10 0.1 10 Figure 7. Gate Charge Characteristics 30 100 P(PK), PEAK TRANSIENT POWER (W) ID, DRAIN CURRENT (A) 10 Figure 8. Capacitance vs Drain to Source Voltage 50 10 1 1 ms THIS AREA IS LIMITED BY rDS(on) 0.
PAGE 5
2.0 0.05 C A B 2X 2.0 1.70 (0.20) 1.00 PIN#1 IDENT 0.05 C TOP VIEW No Traces allowed in this Area 4 6 2X 1.05 2.30 0.10 C 0.47(6X) 0.08 C 1 SIDE VIEW C 0.40(6X) 0.65 RECOMMENDED LAND PATTERN OPT 1 SEATING PLANE (0.15) 3 (0.50) 1.70 PIN #1 IDENT 1 0.45 (0.20) (0.20)4X 3 1.00 6 (6X) 4 (0.50) 1.05 6 4 0.65 1.30 0.10 0.05 BOTTOM VIEW NOTES: A. PACKAGE DOES NOT FULLY CONFORM TO JEDEC MO-229 REGISTRATION B. DIMENSIONS ARE IN MILLIMETERS. C.
PAGE 6
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