Datasheet

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FDMA910PZ Rev.C5

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FDMA910PZ Single P-Channel PowerTrench

MOSFET

June 2014

FDMA910PZ

Single P-Channel PowerTrench

MOSFET

-20 V, -9.4 A, 20 mΩ

Features

 Max r

DS(on)

= 20 mΩ at V

= -4.5 V, I

= -9.4 A

 Max r

DS(on)

= 24 mΩ at V

= -2.5 V, I

= -8.6 A

 Max r

DS(on)

= 34 mΩ at V

= -1.8 V, I

= -7.2 A

 Low Profile - 0.8 mm maximum in the new package MicroFET

2x2 mm

 HBM ESD protection level > 2.8k V typical (Note 3)

 Free from halogenated compounds and antimony oxides

 RoHS Compliant

General Description

This device is designed specifically for battery charge or load

switching in cellular handset and other ultraportable

applications.It features a MOSFET with low on-state resistance

and zener diode protection against ESD. The MicroFET 2X2

package offers exceptional thermal performance for its physical

size and is well suited to linear mode applications.

Pin 1

Drain

Source

MicroFET 2X2 (Bottom View)

Bottom Drain Contact

MOSFET Maximum Ratings T

= 25 °C unless otherwise noted

Thermal Characteristics

Package Marking and Ordering Information

Symbol Parameter Ratings Units

Drain to Source Voltage -20 V

Gate to Source Voltage ±8 V

-Continuous T

= 25°C (Note 1a) -9.4

-Pulsed -45

Power Dissipation T

= 25°C (Note 1a) 2.4

Power Dissipation T

= 25°C (Note 1b) 0.9

, T

STG

Operating and Storage Junction Temperature Range -55 to +150 °C

θJA

Thermal Resistance, Junction to Ambient (Note 1a) 52

°C/W

θJA

Thermal Resistance, Junction to Ambient (Note 1b) 145

Device Marking Device Package Reel Size Tape Width Quantity

910 FDMA910PZ MicroFET 2X2 7” 8 mm 3000 units

Summary of content (7 pages)

PAGE 1
FDMA910PZ Single P-Channel PowerTrench® MOSFET -20 V, -9.4 A, 20 mΩ Features General Description Max rDS(on) = 20 mΩ at VGS = -4.5 V, ID = -9.4 A This device is designed specifically for battery charge or load switching in cellular handset and other ultraportable applications.It features a MOSFET with low on-state resistance and zener diode protection against ESD. The MicroFET 2X2 package offers exceptional thermal performance for its physical size and is well suited to linear mode applications.
PAGE 2
Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = -250 μA, VGS = 0 V ΔBVDSS ΔTJ Breakdown Voltage Temperature Coefficient ID = -250 μA, referenced to 25 °C IDSS Zero Gate Voltage Drain Current VDS = -16 V, VGS = 0 V -1 μA IGSS Gate to Source Leakage Current VGS = ±8 V, VDS = 0 V ±1 μA -1.
PAGE 3
VGS = -4.5 V VGS = -3.5 V VGS = -1.8 V VGS = -2.5 V 30 VGS = -1.5 V 15 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 0 0.0 0.5 1.0 1.5 3 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE -ID, DRAIN CURRENT (A) 45 2.0 VGS = -1.5 V VGS = -1.8 V 2 VGS = -2.5 V 1 VGS = -3.5 V PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 0 0 15 30 -ID, DRAIN CURRENT (A) -VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 1. On-Region Characteristics 60 ID = -9.4 A VGS = -4.5 V rDS(on), DRAIN TO 1.3 1.2 1.1 1.0 0.9 0.
PAGE 4
5000 ID = -9.4 A Ciss VDD = -8 V CAPACITANCE (pF) -VGS, GATE TO SOURCE VOLTAGE (V) 4.5 3.0 VDD = -10 V VDD = -12 V 1.5 1000 Coss Crss f = 1 MHz VGS = 0 V 0.0 0 5 10 15 20 100 0.1 25 1 10 20 -VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) Figure 7. Gate Charge Characteristics Figure 8.
PAGE 5
2 NORMALIZED THERMAL IMPEDANCE, ZθJA 1 0.1 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 0.01 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA SINGLE PULSE o RθJA = 145 C/W 0.001 -4 10 -3 10 -2 10 -1 10 1 10 100 1000 t, RECTANGULAR PULSE DURATION (sec) Figure 12. Junction-to-Ambient Transient Thermal Response Curve ©2012 Fairchild Semiconductor Corporation FDMA910PZ Rev.C5 5 www.fairchildsemi.
PAGE 6
FDMA910PZ Single P-Channel PowerTrench® MOSFET Dimensional Outline and Pad Layout Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
PAGE 7
tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.