Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFDMB2307NZ, MOSFET

April 2014

FDMB2307NZ Rev.C7

www.fairchildsemi.com

FDMB2307NZ Dual Common Drain N-Channel PowerTrench

MOSFET

FDMB2307NZ

Dual Common Drain N-Channel PowerTrench

MOSFET

20 V, 9.7 A, 16.5 mΩ

Features

 Max r

S1S2(on)

= 16.5 mΩ at V

= 4.5 V, I

= 8 A

 Max r

S1S2(on)

= 18 mΩ at V

= 4.2 V, I

= 7.4 A

 Max r

S1S2(on)

= 21 mΩ at V

= 3.1 V, I

= 7 A

 Max r

S1S2(on)

= 24 mΩ at V

= 2.5 V, I

= 6.7 A

 Low Profile - 0.8 mm maximum - in the new package

MicroFET 2x3 mm

 HBM ESD protection level > 2 kV (Note 3)

 RoHS Compliant

General Description

This device is designed specifically as a single package solution

for Li-Ion battery pack protection circuit and other ultra-portable

applications. It features two common drain N-channel

MOSFETs, which enables bidirectional current flow, on

Fairchild’s advanced PowerTrench

process with state of the art

MicroFET Leadframe, the FDMB2307NZ minimizes both PCB

space and r

S1S2(on)

Application

 Li-Ion Battery Pack

MLP 2x3

S1S2

S2 S1

G1S1S1

G2S2S2

D1/D2

Pin 1

Bottom Top

MOSFET Maximum Ratings T

= 25°C unless otherwise noted

Thermal Characteristics

Package Marking and Ordering Information

Symbol Parameter Ratings Units

S1S2

Source1 to Source2 Voltage 20 V

Gate to Source Voltage (Note 4) ±12 V

S1S2

Source1 to Source2 Current -Continuous T

= 25°C (Note 1a) 9.7

-Pulsed 40

Power Dissipation T

= 25 °C (Note 1a) 2.2

Power Dissipation T

= 25 °C (Note 1b) 0.8

, T

STG

Operating and Storage Junction Temperature Range -55 to +150 °C

θJA

Thermal Resistance, Junction to Ambient(Dual Operation) (Note 1a) 57

°C/W

θJA

Thermal Resistance, Junction to Ambient(Dual Operation) (Note 1b) 161

Device Marking Device Package Reel Size Tape Width Quantity

307 FDMB2307NZ MLP 2x3 7’’ 8 mm 3000 units

Summary of content (7 pages)

PAGE 1
FDMB2307NZ Dual Common Drain N-Channel PowerTrench® MOSFET 20 V, 9.7 A, 16.5 mΩ Features General Description Max rS1S2(on) = 16.5 mΩ at VGS = 4.5 V, ID = 8 A This device is designed specifically as a single package solution Max rS1S2(on) = 18 mΩ at VGS = 4.2 V, ID = 7.4 A for Li-Ion battery pack protection circuit and other ultra-portable Max rS1S2(on) = 21 mΩ at VGS = 3.1 V, ID = 7 A applications. Max rS1S2(on) = 24 mΩ at VGS = 2.5 V, ID = 6.
PAGE 2
Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics IS1S2 Zero Gate Voltage Source1 to Source2 Current VS1S2 = 16 V, VGS = 0 V 1 μA IGSS Gate to Source Leakage Current VGS = 12 V, VS1S2 = 0 V 10 μA V On Characteristics VGS(th) Gate to Source Threshold Voltage VGS = VS1S2, IS1S2 = 250 μA 0.6 1 1.5 VGS = 4.5 V, IS1S2 = 8 A 10.5 13.5 16.5 VGS = 4.2 V, IS1S2 = 7.4 A rS1S2(on) gFS Static Source1 to Source2 On Resistance Forward Transconductance 11 14 18 11.
PAGE 3
IS1S2, SOURCE1 TO SOURCE2 CURRENT (A) IS1S2, SOURCE1 TO SOURCE2 CURRENT (A) 40 VG1S1 = 4.5 V VG1S1 = 4.2 V 30 VG1S1 = 3.1 V VG1S1 = 2.5 V 20 10 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX VG2S2 = 4.5 V 0 0.0 0.2 0.4 0.6 VS1S2, SOURCE1 TO SOURCE2 VOLTAGE (V) 0.8 40 VGS = 4.5 V VGS = 4.2 V 30 VGS = 3.1 V VGS = 2.5 V 20 10 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 0 0.0 1.5 VG1S1 = 3.1 V 1.0 VG1S1 = 4.2 V VG1S1 = 4.5 V PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX VG2S2 = 4.5 V 0.
PAGE 4
Ifss, SOURCE1 TO SOURCE2 FORWARD CURRENT (A) IS1S2, SOURCE1 TO SOURCE2 CURRENT (A) 40 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 30 VS1S2 = 5 V TJ = 150 oC 20 TJ = 25 oC 10 TJ = -55 oC 0 0.5 1.0 1.5 2.0 100 VG1S1 = 0 V, VG2S2 = 4.5 V 10 TJ = 150 oC 1 0.1 0.01 0.001 0.0 VGS, GATE TO SOURCE VOLTAGE (V) 0.2 0.4 0.6 0.8 1.0 1.2 Figure 8.
PAGE 5
1000 P(PK), PEAK TRANSIENT POWER (W) SINGLE PULSE o RθJA = 161 C/W o TA = 25 C 100 10 1 0.5 -3 10 -2 -1 10 10 1 10 100 1000 t, PULSE WIDTH (sec) Figure 13. Single Pulse Maximum Power Dissipation 2 DUTY CYCLE-DESCENDING ORDER NORMALIZED THERMAL IMPEDANCE, ZθJA 1 0.1 D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 0.01 t2 SINGLE PULSE NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA o RθJA = 161 C/W 0.
PAGE 6
FDMB2307NZ Dual Common Drain N-Channel PowerTrench® MOSFET Dimensional Outline and Pad Layout Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
PAGE 7
tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.