Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFDMC2512SDC, MOSFET

FDMC2512SDC N-Channel Dual Cool

PowerTrench

SyncFET

FDMC2512SDC Rev.C2

www.fairchildsemi.com

July 2010

FDMC2512SDC

N-Channel Dual Cool

PowerTrench

SyncFET

25 V, 40 A, 2.0 mΩ

Features

 Dual Cool

Top Side Cooling PQFN package

 Max r

DS(on)

= 2.0 mΩ at V

= 10 V, I

= 27 A

 Max r

DS(on)

= 2.95 mΩ at V

= 4.5 V, I

= 22 A

 High performance technology for extremely low r

DS(on)

 SyncFET Schottky Body Diode

 RoHS Compliant

General Description

This N-Channel MOSFET is produced using Fairchild

Semiconductor’s advanced PowerTrench

process.

Advancements in both silicon and Dual Cool

package

technologies have been combined to offer the lowest r

DS(on)

while maintaining excellent switching performance by extremely

low Junction-to-Ambient thermal resistance. This device has the

added benefit of an efficient monolithic Schottky body diode.

Applications

 Synchronous Rectifier for DC/DC Converters

 Telecom Secondary Side Rectification

 High End Server/Workstation Vcore Low Side

Top

Power 33

Bottom

Pin 1

MOSFET Maximum Ratings T

= 25°C unless otherwise noted

Thermal Characteristics

Package Marking and Ordering Information

Symbol Parameter Ratings Units

Drain to Source Voltage 25 V

Gate to Source Voltage (Note 4) ±20 V

Drain Current -Continuous (Package limited) T

= 25 °C 40

-Continuous (Silicon limited) T

= 25 °C 148

-Continuous T

= 25 °C (Note 1a) 32

-Pulsed 200

Single Pulse Avalanche Energy (Note 3) 144 mJ

dv/dt Peak Diode Recovery dv/dt (Note 5) 1.8 V/ns

Power Dissipation T

= 25 °C 66

Power Dissipation T

= 25 °C (Note 1a) 3.0

, T

STG

Operating and Storage Junction Temperature Range -55 to +150 °C

θJC

Thermal Resistance, Junction to Case (Top Source) 4.5

°C/W

θJC

Thermal Resistance, Junction to Case (Bottom Drain) 1.9

θJA

Thermal Resistance, Junction to Ambient (Note 1a) 42

θJA

Thermal Resistance, Junction to Ambient (Note 1b) 105

θJA

Thermal Resistance, Junction to Ambient (Note 1i) 17

θJA

Thermal Resistance, Junction to Ambient (Note 1j) 26

θJA

Thermal Resistance, Junction to Ambient (Note 1k) 12

Device Marking Device Package Reel Size Tape Width Quantity

2512S FDMC2512SDC Dual Cool

Power 33 13’’ 12 mm 3000 units

Summary of content (9 pages)

PAGE 1
FDMC2512SDC N-Channel Dual CoolTM PowerTrench® SyncFETTM 25 V, 40 A, 2.0 mΩ Features Dual CoolTM General Description Top Side Cooling PQFN package SyncFET Schottky Body Diode This N-Channel MOSFET is produced using Fairchild Semiconductor’s advanced PowerTrench® process. Advancements in both silicon and Dual CoolTM package technologies have been combined to offer the lowest rDS(on) while maintaining excellent switching performance by extremely low Junction-to-Ambient thermal resistance.
PAGE 2
Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = 1 mA, VGS = 0 V ΔBVDSS ΔTJ Breakdown Voltage Temperature Coefficient 25 V ID = 10 mA, referenced to 25 °C IDSS Zero Gate Voltage Drain Current VDS = 20 V, VGS = 0 V 500 μA IGSS Gate to Source Leakage Current, Forward VGS = 20 V, VDS = 0 V 100 nA 2.
PAGE 3
RθJC Thermal Resistance, Junction to Case (Top Source) 4.5 RθJC Thermal Resistance, Junction to Case (Bottom Drain) 1.
PAGE 4
VGS = 10 V VGS = 4.5 V VGS = 3.3 V ID, DRAIN CURRENT (A) 90 6 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 120 VGS = 3 V PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 60 VGS = 2.7 V 30 VGS = 2.7 V 5 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 4 VGS = 3 V 3 VGS = 3.3 V 2 VGS = 4.5 V 1 VGS = 10 V 0 0 0 1 2 3 4 0 5 30 ID = 27 A VGS = 10 V rDS(on), DRAIN TO 1.3 1.2 1.1 1.0 0.9 0.8 -75 SOURCE ON-RESISTANCE (mΩ) NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 120 10 1.
PAGE 5
000 IDSS = 27 A Ciss 8 CAPACITANCE (pF) VGS, GATE TO SOURCE VOLTAGE (V) 10 VDD = 13 V 6 VDD = 10 V VDD = 16 V 4 1000 Coss 2 100 f = 1 MHz 0 0 10 20 30 40 50 0.1 50 1 Figure 7. Gate Charge Characteristics Figure 8. Capacitance vs Drain to Source Voltage 50 160 o RθJC = 1.9 C/W VGS = 10 V ID, DRAIN CURRENT (A) IAS, AVALANCHE CURRENT (A) 30 10 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) TJ = 25 oC 10 TJ = 100 oC TJ = 125 oC 120 VGS = 4.
PAGE 6
NORMALIZED THERMAL IMPEDANCE, ZθJA 2 1 0.1 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM 0.01 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA SINGLE PULSE o RθJA = 105 C/W 0.001 0.0005 -4 10 -3 10 -2 10 -1 10 1 10 100 1000 t, RECTANGULAR PULSE DURATION (sec) Figure 13. Junction-to-Ambient Transient Thermal Response Curve ©2010 Fairchild Semiconductor Corporation FDMC2512SDC Rev.C2 6 www.fairchildsemi.
PAGE 7
SyncFET Schottky body diode Characteristics Schottky barrier diodes exhibit significant leakage at high temperature and high reverse voltage. This will increase the power in the device. Fairchild’s SyncFET process embeds a Schottky diode in parallel with PowerTrench MOSFET. This diode exhibits similar characteristics to a discrete external Schottky diode in parallel with a MOSFET. Figure 14 shows the reverse recovery characteristic of the FDMC2512SDC.
PAGE 8
FDMC2512SDC N-Channel Dual CoolTM PowerTrench® SyncFETTM Dimensional Outline and Pad Layout ©2010 Fairchild Semiconductor Corporation FDMC2512SDC Rev.C2 8 www.fairchildsemi.
PAGE 9
*Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.