Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFDMC4435BZ, MOSFET

May 2014

FDMC4435BZ Rev.D3

www.fairchildsemi.com

FDMC4435BZ P-Channel Power Trench

MOSFET

FDMC4435BZ

P-Channel Power Trench

MOSFET

-30 V, -18 A, 20 mΩ

Features

 Max r

DS(on)

= 20 mΩ at V

= -10 V, I

= -8.5 A

 Max r

DS(on)

= 37 mΩ at V

= -4.5 V, I

= -6.3 A

 Extended V

GSS

range (-25 V) for battery applications

 High performance trench technology for extremely low r

DS(on)

 High power and current handling capability

 HBM ESD protection level >7 kV typical (Note 4)

 100% UIL Tested

 Termination is Lead-free and RoHS Compliant

General Description

This P-Channel MOSFET is produced using Fairchild

Semiconductor’s advanced Power Trench

process that has

been especially tailored to minimize the on-state resistance. This

device is well suited for Power Management and load

switching applications common in Notebook Computers and

Portable Battery Packs

Applications

 High side in DC - DC Buck Converters

 Notebook battery power management

 Load switch in Notebook

MOSFET Maximum Ratings T

= 25 °C unless otherwise noted

Thermal Characteristics

Package Marking and Ordering Information

Symbol Parameter Ratings Units

Drain to Source Voltage -30 V

Gate to Source Voltage ±25 V

Drain Current -Continuous T

= 25 °C -18

A -Continuous T

= 25 °C (Note 1a) -8.5

-Pulsed -50

Single Pulse Avalanche Energy (Note 3) 32 mJ

Power Dissipation T

= 25 °C 31

Power Dissipation T

= 25 °C (Note 1a) 2.3

, T

STG

Operating and Storage Junction Temperature Range -55 to +150 °C

θJC

Thermal Resistance, Junction to Case 4

°C/W

θJA

Thermal Resistance, Junction to Ambient (Note 1a) 53

Device Marking Device Package Reel Size Tape Width Quantity

FDMC4435BZ FDMC4435BZ MLP 3.3X3.3 13 ’’ 12 mm 3000 units

Bottom

Top

Pin 1

MLP 3.3x3.3

Summary of content (7 pages)

PAGE 1
FDMC4435BZ P-Channel Power Trench® MOSFET -30 V, -18 A, 20 mΩ Features General Description Max rDS(on) = 20 mΩ at VGS = -10 V, ID = -8.5 A This P-Channel MOSFET is produced using Fairchild Semiconductor’s advanced Power Trench® process that has been especially tailored to minimize the on-state resistance. This device is well suited for Power Management and load switching applications common in Notebook Computers and Portable Battery Packs. Max rDS(on) = 37 mΩ at VGS = -4.5 V, ID = -6.
PAGE 2
Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = -250 μA, VGS = 0 V ΔBVDSS ΔTJ Breakdown Voltage Temperature Coefficient ID = -250 μA, referenced to 25 °C IDSS Zero Gate Voltage Drain Current IGSS Gate to Source Leakage Current -30 V 21 VDS = -24 V, VGS = 0 V, mV/°C -1 TJ = 125 °C -100 VGS = ±25 V, VDS = 0 V μA ±10 μA -3.
PAGE 3
4.0 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 50 -ID, DRAIN CURRENT (A) VGS = -4.5V 40 VGS = -5V VGS = -10V 30 VGS = - 4V 20 VGS = -3.5V 10 PULSE DURATION = 80μs DUTY CYCLE = 0.5%MAX 0 0 1 2 3 PULSE DURATION = 80μs DUTY CYCLE = 0.5%MAX 3.5 VGS = -3.5V 3.0 VGS = -4V 2.5 VGS = -4.5V 2.0 1.5 VGS = -5V 1.0 VGS = -10V 0.5 4 0 10 -VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 1. On-Region Characteristics rDS(on), DRAIN TO 0.
PAGE 4
-VGS, GATE TO SOURCE VOLTAGE(V) 10 10000 ID = -8.5A 8 Ciss CAPACITANCE (pF) VDD = -10V 6 VDD = -15V 4 VDD = -20V 2 1000 Coss Crss 100 f = 1MHz VGS = 0V 0 0 10 20 30 10 0.1 40 Qg, GATE CHARGE(nC) Figure 7. Gate Charge Characteristics 30 40 -ID, DRAIN CURRENT (A) -IAS, AVALANCHE CURRENT(A) 10 Figure 8. Capacitance vs Drain to Source Voltage 20 10 TJ = 25oC TJ = 125oC VGS = -10V 30 VGS = -4.5V 20 10 Limited by Package o RθJC = 4 C/W 1 0.001 0.01 0.
PAGE 5
P(PK), PEAK TRANSIENT POWER (W) 100 VGS = -10V 10 SINGLE PULSE o RθJA = 125 C/W o TA = 25 C 1 0.5 -3 10 -2 -1 10 10 1 10 100 1000 t, PULSE WIDTH (sec) r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE Figure 13. Single Pulse Maximum Power Dissipation 2 1 0.1 0.01 -3 10 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.
PAGE 6
FDMC4435BZ P-Channel Power Trench® MOSFET Dimensional Outline and Pad Layout Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
PAGE 7
tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.