Datasheet

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©2009 Fairchild Semiconductor Corporation
FDMC6679AZ Rev.D4
FDMC6679AZ P-Channel PowerTrench
®
MOSFET
Electrical Characteristics T
J
= 25 °C unless otherwise noted
Off Characteristics
On Characteristics
Dynamic Characteristics
Switching Characteristics
Drain-Source Diode Characteristics
Symbol Parameter Test Conditions Min Typ Max Units
BV
DSS
Drain to Source Breakdown Voltage I
D
= -250 μA, V
GS
= 0 V -30 V
ΔBV
DSS
ΔT
J
Breakdown Voltage Temperature
Coefficient
I
D
= -250 μA, referenced to 25 °C 29 mV/°C
I
DSS
Zero Gate Voltage Drain Current
V
DS
= -24 V, -1
μA
V
GS
= 0 V, T
J
= 125 °C -100
I
GSS
Gate to Source Leakage Current V
GS
= ±25 V, V
DS
= 0 V ±10 μA
V
GS(th)
Gate to Source Threshold Voltage V
GS
= V
DS
, I
D
= -250 μA-1-1.8-3V
ΔV
GS(th)
ΔT
J
Gate to Source Threshold Voltage
Temperature Coefficient
I
D
= -250 μA, referenced to 25 °C -7 mV/°C
r
DS(on)
Static Drain to Source On Resistance
V
GS
= -10 V, I
D
= -11.5 A 8.6 10
mΩV
GS
= -4.5 V, I
D
= -8.5 A 12 18
V
GS
= -10 V, I
D
= -11.5 A, T
J
= 125 °C 12 15
g
FS
Forward Transconductance V
DS
= -5 V, I
D
= -11.5 A 46 S
C
iss
Input Capacitance
V
DS
= -15 V, V
GS
= 0 V,
f = 1 MHz
2985 3970 pF
C
oss
Output Capacitance 570 755 pF
C
rss
Reverse Transfer Capacitance 500 750 pF
t
d(on)
Turn-On Delay Time
V
DD
= -15 V, I
D
= -11.5 A,
V
GS
= -10 V, R
GEN
= 6 Ω
12 21 ns
t
r
Rise Time 14 25 ns
t
d(off)
Turn-Off Delay Time 63 100 ns
t
f
Fall Time 46 73 ns
Q
g
Total Gate Charge V
GS
= 0 V to -10 V
V
DD
= -15 V,
I
D
= -11.5 A
65 91 nC
Q
g
Total Gate Charge V
GS
= 0 V to -5 V 37 52 nC
Q
gs
Gate to Source Charge 8.7 nC
Q
gd
Gate to Drain “Miller” Charge 17 nC
V
SD
Source to Drain Diode Forward Voltage
V
GS
= 0 V, I
S
= -11.5 A (Note 2) 0.83 1.30
V
V
GS
= 0 V, I
S
= -1.6 A (Note 2) 0.71 1.20
t
rr
Reverse Recovery Time
I
F
= -11.5 A, di/dt = 100 A/μs
31 49 ns
Q
rr
Reverse Recovery Charge 16 28 nC
NOTES:
1. R
θJA
is determined with the device mounted on a 1 in
2
pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. R
θJC
is guaranteed by design while R
θCA
is determined by
the user's board design.
2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0 %.
3. The diode connected between the gate and source servers only as protection against ESD. No gate overvoltage rating is implied.
a. 53 °C/W when mounted on
a 1 in
2
pad of 2 oz copper
b.125 °C/W when mounted on
a minimum pad of 2 oz copper