Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFDMC7208S, MOSFET

July 2013

FDMC7208S Dual N-Channel PowerTrench

MOSFET

FDMC7208S Rev.C3

FDMC7208S

Dual N-Channel PowerTrench

MOSFET

Q1: 30 V, 12 A, 9.0 mΩ Q2: 30 V, 16 A, 6.4 mΩ

Features

Q1: N-Channel

 Max r

DS(on)

= 9.0 mΩ at V

= 10 V, I

= 12 A

 Max r

DS(on)

= 11.0 mΩ at V

= 4.5 V, I

= 11 A

Q2: N-Channel

 Max r

DS(on)

= 6.4 mΩ at V

= 10 V, I

= 16 A

 Max r

DS(on)

= 7.5 mΩ at V

= 4.5 V, I

= 13.5 A

 Termination is Lead-free and RoHS Compliant

General Description

This device includes two 30V N-Channel MOSFETs in a dual

Power 33 (3 mm X 3 mm MLP) package. The package is en-

hanced for exceptional thermal performance.

Applications

 Computing

 Communications

 General Purpose Point of Load

 Notebook System

Power 33

Pin 1

S1S1

S2S2

MOSFET Maximum Ratings T

= 25 °C unless otherwise noted

Thermal Characteristics

Package Marking and Ordering Information

Symbol Parameter Q1 Q2 Units

Drain to Source Voltage 30 30 V

Gate to Source Voltage (Note 4) ±20 ±12 V

Drain Current -Continuous (Package limited) T

= 25 °C 22 26

A -Continuous T

= 25 °C 12

-Pulsed 60 80

Single Pulse Avalanche Energy (Note 3) 21 21 mJ

Power Dissipation for Single Operation T

= 25 °C 1.9

1.9

Power Dissipation for Single Operation T

= 25 °C 0.8

0.8

, T

STG

Operating and Storage Junction Temperature Range -55 to +150 °C

θJA

Thermal Resistance, Junction to Ambient 65

°C/W

θJA

Thermal Resistance, Junction to Ambient 155

155

Device Marking Device Package Reel Size Tape Width Quantity

FDMC7208S FDMC7208S Power 33 13 ” 12 mm 3000 units

Summary of content (12 pages)

PAGE 1
FDMC7208S Dual N-Channel PowerTrench® MOSFET Q1: 30 V, 12 A, 9.0 mΩ Q2: 30 V, 16 A, 6.4 mΩ Features General Description Q1: N-Channel This device includes two 30V N-Channel MOSFETs in a dual Power 33 (3 mm X 3 mm MLP) package. The package is enhanced for exceptional thermal performance. Max rDS(on) = 9.0 mΩ at VGS = 10 V, ID = 12 A Max rDS(on) = 11.0 mΩ at VGS = 4.5 V, ID = 11 A Applications Q2: N-Channel Max rDS(on) = 6.4 mΩ at VGS = 10 V, ID = 16 A Computing Max rDS(on) = 7.
PAGE 2
Symbol Parameter Test Conditions Type Min 30 30 Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V ID = 1 mA, VGS = 0 V Q1 Q2 ΔBVDSS ΔTJ Breakdown Voltage Temperature Coefficient ID = 250 μA, referenced to 25 °C ID = 10 mA, referenced to 25 °C Q1 Q2 IDSS Zero Gate Voltage Drain Current VDS = 24 V, VGS = 0 V Q1 Q2 1 500 μA IGSS Gate to Source Leakage Current, Forward VGS = 20 V, VDS= 0 V VGS = 12 V, VDS= 0 V Q1 Q2 100 100 nA 3.0 3.
PAGE 3
Symbol Parameter Test Conditions Type Min Typ Max Units Q1 Q1 Q2 Q2 0.72 0.82 0.70 0.82 1.2 1.2 1.2 1.2 V Q1 Q2 21 21 34 33 ns Q1 Q2 6 16 12 28 nC Drain-Source Diode Characteristics VSD VGS = 0 V, IS = 2 A V = 0 V, IS = 12 A Source to Drain Diode Forward Voltage GS VGS = 0 V, IS = 2 A VGS = 0 V, IS = 16 A trr Reverse Recovery Time Qrr Reverse Recovery Charge (Note 2) (Note 2) (Note 2) (Note 2) Q1 IF = 12 A, di/dt = 100 A/μs Q2 IF = 16 A, di/dt = 300 A/μs Notes: 1.
PAGE 4
60 5 VGS = 4.5 V 50 ID, DRAIN CURRENT (A) NORMALIZED DRAIN TO SOURCE ON-RESISTANCE VGS = 10 V VGS = 3.5 V 40 VGS = 4 V 30 VGS = 3 V 20 10 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 0 0 1 2 3 4 4 VGS = 3.5 V 3 VGS = 4 V 2 1 0 5 0 10 20 30 40 50 60 ID, DRAIN CURRENT (A) Figure 1. On Region Characteristics Figure 2. Normalized On-Resistance vs Drain Current and Gate Voltage 40 ID = 12 A VGS = 10 V rDS(on), DRAIN TO 1.4 1.2 1.0 0.8 0.6 -75 SOURCE ON-RESISTANCE (mΩ) 1.
PAGE 5
VGS, GATE TO SOURCE VOLTAGE (V) 10 2000 ID = 12 A 8 CAPACITANCE (pF) VDD = 15 V 6 VDD = 10 V 4 VDD = 20 V Coss 100 Crss f = 1 MHz VGS = 0 V 2 0 0 5 10 10 0.1 15 1 10 30 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) Figure 7. Gate Charge Characteristics Figure 8. Capacitance vs Drain to Source Voltage 40 100 ID, DRAIN CURRENT (A) IAS, AVALANCHE CURRENT (A) Ciss 1000 10 TJ = 25 oC TJ = 100 oC TJ = 125 oC 10 1 0.1 TA = 25 oC 0.1 1 10 0.01 0.
PAGE 6
2 DUTY CYCLE-DESCENDING ORDER NORMALIZED THERMAL IMPEDANCE, ZθJA 1 0.1 D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 SINGLE PULSE NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC x RθJc + TC o RθJA = 155 C/W (Note 1b) 0.01 0.005 -3 10 -2 10 -1 0 10 10 1 10 100 1000 t, RECTANGULAR PULSE DURATION (sec) Figure 12. Junction-to-Ambient Transient Thermal Response Curve ©2012 Fairchild Semiconductor Corporation FDMC7208S Rev.C3 6 www.fairchildsemi.
PAGE 7
80 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 5 ID, DRAIN CURRENT (A) VGS = 10 V VGS = 4.5 V 60 VGS = 4 V VGS = 3.5 V VGS = 3 V 40 20 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 0 0.0 0.5 1.0 1.5 2.0 2.5 VGS = 3 V 4 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 3 VGS = 3.5 V 2 1 0 3.0 0 20 VDS, DRAIN TO SOURCE VOLTAGE (V) 60 80 Figure 15. Normalized on-Resistance vs Drain Current and Gate Voltage 30 ID = 16 A VGS = 10 V 1.4 rDS(on), DRAIN TO 1.3 1.2 1.1 1.0 0.9 0.8 0.
PAGE 8
3000 VGS, GATE TO SOURCE VOLTAGE (V) 10 ID = 16 A Ciss 1000 CAPACITANCE (pF) 8 VDD = 15 V 6 VDD = 10 V 4 VDD = 20 V Coss 100 2 10 0.1 0 0 6 12 18 24 30 1 10 30 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) Figure 21. Capacitance vs Drain to Source Voltage Figure 20. Gate Charge Characteristics 40 100 10 ID, DRAIN CURRENT (A) IAS, AVALANCHE CURRENT (A) Crss f = 1 MHz VGS = 0 V TJ = 25 oC TJ = 100 oC TJ = 125 oC 10 1 ms 1 0.
PAGE 9
2 DUTY CYCLE-DESCENDING ORDER NORMALIZED THERMAL IMPEDANCE, ZθJA 1 0.1 D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 SINGLE PULSE NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC x RθJC + TC o RθJA = 155 C/W (Note 1b) 0.01 0.005 -3 10 -2 10 -1 0 10 10 1 10 100 1000 t, RECTANGULAR PULSE DURATION (sec) Figure 26. Junction-to-Ambient Transient Thermal Response Curve ©2012 Fairchild Semiconductor Corporation FDMC7208S Rev.C3 9 www.fairchildsemi.
PAGE 10
SyncFETTM Schottky body diode Characteristics Fairchild’s SyncFETTM process embeds a Schottky diode in parallel with PowerTrench MOSFET. This diode exhibits similar characteristics to a discrete external Schottky diode in parallel with a MOSFET. Figure 27 shows the reverses recovery characteristic of the FDMC7208S. Schottky barrier diodes exhibit significant leakage at high temperature and high reverse voltage. This will increase the power in the device.
PAGE 11
FDMC7208S Dual N-Channel PowerTrench® MOSFET Dimensional Outline and Pad Layout ©2012 Fairchild Semiconductor Corporation FDMC7208S Rev.C3 11 www.fairchildsemi.
PAGE 12
tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.