Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFDMC7570S, MOSFET

FDMC7570S N-Channel Power Trench

SyncFET

FDMC7570S Rev.C

www.fairchildsemi.com

December 2009

FDMC7570S

N-Channel Power Trench

SyncFET

25 V, 40 A, 2 mΩ

Features

 Max r

DS(on)

= 2 mΩ at V

= 10 V, I

= 27 A

 Max r

DS(on)

= 2.9 mΩ at V

= 4.5 V, I

= 21.5 A

 Advanced Package and Combination for low r

DS(on)

and high

efficiency

 SyncFET Schottky Body Diode

 100% UIL Tested

 RoHS Compliant

General Description

The FDMC7570S has been designed to minimize losses in

power conversion application. Advancements in both silicon and

package technologies have been combined to offer the lowest

DS(on)

while maintaining excellent switching performance. This

device has the added benefit of an efficient monolithic Schottky

body diode.

Applications

 Synchronous Rectifier for DC/DC Converters

 Notebook Vcore/ GPU low side switch

 Networking Point of Load low side switch

 Telecom secondary side rectification

MOSFET Maximum Ratings T

= 25 °C unless otherwise noted

Thermal Characteristics

Package Marking and Ordering Information

Symbol Parameter Ratings Units

Drain to Source Voltage 25 V

Gate to Source Voltage (Note 4) ±20 V

Drain Current -Continuous (Package limited) T

= 25 °C 40

-Continuous (Silicon limited) T

= 25 °C 132

-Continuous T

= 25 °C (Note 1a) 27

-Pulsed 120

Single Pulse Avalanche Energy (Note 3) 144 mJ

Power Dissipation T

= 25 °C 59

Power Dissipation T

= 25 °C (Note 1a) 2.3

, T

STG

Operating and Storage Junction Temperature Range -55 to +150 °C

θJC

Thermal Resistance, Junction to Case 2.1

°C/W

θJA

Thermal Resistance, Junction to Ambient (Note 1a) 53

Device Marking Device Package Reel Size Tape Width Quantity

FDMC7570S FDMC7570S Power 33 13 ’’ 12 mm 3000 units

Top

Power 33

Bottom

Pin 1

Summary of content (8 pages)

PAGE 1
FDMC7570S N-Channel Power Trench® SyncFETTM 25 V, 40 A, 2 mΩ Features General Description Max rDS(on) = 2 mΩ at VGS = 10 V, ID = 27 A The FDMC7570S has been designed to minimize losses in Max rDS(on) = 2.9 mΩ at VGS = 4.5 V, ID = 21.5 A power conversion application. Advancements in both silicon and package technologies have been combined to offer the lowest Advanced Package and Combination for low rDS(on) and high efficiency rDS(on) while maintaining excellent switching performance.
PAGE 2
Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = 1 mA, VGS = 0 V ∆BVDSS ∆TJ Breakdown Voltage Temperature Coefficient 25 V ID = 10 mA, referenced to 25 °C IDSS Zero Gate Voltage Drain Current VDS = 20 V, VGS = 0 V 500 µA IGSS Gate to Source Leakage Current, Forward VGS = 20 V, VDS = 0 V 100 nA 3 V 21 mV/°C On Characteristics VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 1 mA ∆VGS(th) ∆TJ Gate to So
PAGE 3
VGS = 10 V VGS = 4.5 V VGS = 3.3 V ID, DRAIN CURRENT (A) 90 6 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 120 VGS = 3 V PULSE DURATION = 80 µs DUTY CYCLE = 0.5% MAX 60 VGS = 2.7 V 30 VGS = 2.7 V 5 PULSE DURATION = 80 µs DUTY CYCLE = 0.5% MAX 4 VGS = 3 V 3 VGS = 3.3 V 2 VGS = 4.5 V 1 VGS = 10 V 0 0 0 1 2 3 4 0 5 30 120 10 ID = 27 A VGS = 10 V 1.4 rDS(on), DRAIN TO 1.3 1.2 1.1 1.0 0.9 0.8 -75 SOURCE ON-RESISTANCE (mΩ) 1.5 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 90 Figure 2.
PAGE 4
5000 IDSS = 27 A Ciss 8 CAPACITANCE (pF) VGS, GATE TO SOURCE VOLTAGE (V) 10 VDD = 13 V 6 VDD = 10 V VDD = 16 V 4 1000 Coss 2 100 f = 1 MHz 0 0 10 20 30 40 50 0.1 50 Figure 7. Gate Charge Characteristics 30 10 Figure 8. Capacitance vs Drain to Source Voltage 135 ID, DRAIN CURRENT (A) 50 IAS, AVALANCHE CURRENT (A) 1 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) TJ = 25 oC 10 TJ = 100 oC TJ = 125 oC VGS = 10 V 90 VGS = 4.5 V 45 o RθJC = 2.
PAGE 5
NORMALIZED THERMAL IMPEDANCE, ZθJA 2 1 0.1 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM 0.01 t1 t2 SINGLE PULSE NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA o RθJA = 125 C/W 0.001 0.0005 -4 10 -3 10 -2 10 -1 10 1 10 100 1000 t, RECTANGULAR PULSE DURATION (sec) Figure 13. Junction-to-Ambient Transient Thermal Response Curve FDMC7570S Rev.C 5 www.fairchildsemi.
PAGE 6
SyncFET Schottky body diode Characteristics Schottky barrier diodes exhibit significant leakage at high temperature and high reverse voltage. This will increase the power in the device. Fairchild’s SyncFET process embeds a Schottky diode in parallel with PowerTrench MOSFET. This diode exhibits similar characteristics to a discrete external Schottky diode in parallel with a MOSFET. Figure 14 shows the reverses recovery characteristic of the FDMC7570S.
PAGE 7
FDMC7570S N-Channel Power Trench® SyncFETTM Dimensional Outline and Pad Layout FDMC7570S Rev.C 7 www.fairchildsemi.
PAGE 8
tm tm tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.