Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFDMC7660, MOSFET

June 2012

FDMC7660 Rev.C5

www.fairchildsemi.com

FDMC7660 N-Channel PowerTrench

MOSFET

FDMC7660

N-Channel PowerTrench

MOSFET

30 V, 20 A, 2.2 mΩ

Features

 Max r

DS(on)

= 2.2 mΩ at V

= 10 V, I

= 20 A

 Max r

DS(on)

= 3.3 mΩ at V

= 4.5 V, I

= 18 A

 High performance technology for extremely low r

DS(on)

 Termination is Lead-free and RoHS Compliant

General Description

This N-Channel MOSFET is produced using Fairchild

Semiconductor’s advanced Power

Trench

process that has

been especially tailored to minimize the on-state resistance.

This

device is well suited for Power Management and load switching

applications common in Notebook Computers and Portable

Battery Packs.

Applications

 DC - DC Buck Converters

 Point of Load

 High Efficiency Load Switch and Low Side Switching

Top

Power 33

Bottom

Pin 1

MOSFET Maximum Ratings T

= 25°C unless otherwise noted

Thermal Characteristics

Package Marking and Ordering Information

Symbol Parameter Ratings Units

Drain to Source Voltage 30 V

Gate to Source Voltage (Note 4) ±20 V

Drain Current -Continuous (Package limited) T

= 25°C 40

-Continuous (Silicon limited) T

= 25°C 100

-Continuous T

= 25°C (Note 1a) 20

-Pulsed 200

Single Pulse Avalanche Energy (Note 3) 200 mJ

Power Dissipation T

= 25°C 41

Power Dissipation T

= 25°C (Note 1a) 2.3

, T

STG

Operating and Storage Junction Temperature Range -55 to + 150 °C

θJC

Thermal Resistance, Junction to Case 3

°C/W

θJA

Thermal Resistance, Junction to Ambient (Note 1a) 53

Device Marking Device Package Reel Size Tape Width Quantity

FDMC7660 FDMC7660 Power 33 13’’ 12

mm 3000 units

Summary of content (7 pages)

PAGE 1
FDMC7660 N-Channel PowerTrench® MOSFET 30 V, 20 A, 2.2 mΩ Features General Description Max rDS(on) = 2.2 mΩ at VGS = 10 V, ID = 20 A This N-Channel MOSFET is produced using Fairchild Semiconductor’s advanced PowerTrench® process that has been especially tailored to minimize the on-state resistance. This device is well suited for Power Management and load switching applications common in Notebook Computers and Portable Battery Packs. Max rDS(on) = 3.3 mΩ at VGS = 4.
PAGE 2
Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V ΔBVDSS ΔTJ Breakdown Voltage Temperature Coefficient ID = 250 μA, referenced to 25°C IDSS Zero Gate Voltage Drain Current VDS = 24 V, VGS = 0 V 1 μA IGSS Gate to Source Leakage Current VGS = 20 V, VDS = 0 V 100 nA 2.
PAGE 3
.0 200 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE ID, DRAIN CURRENT (A) PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX VGS = 10 V 150 VGS = 4.5 V VGS = 4 V 100 VGS = 3.5 V 50 VGS = 3 V 0 0.0 0.5 1.0 1.5 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 2.5 VGS = 3 V VGS = 3.5 V 2.0 VGS = 4 V 1.5 1.0 2.0 0 50 100 ID, DRAIN CURRENT (A) VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 1. On Region Characteristics 200 15 ID = 20 A VGS = 10 V rDS(on), DRAIN TO 1.4 1.2 1.0 0.
PAGE 4
10 ID = 20 A Ciss 8 CAPACITANCE (nF) VGS, GATE TO SOURCE VOLTAGE (V) 10 VDD = 10 V 6 VDD = 15 V 4 VDD = 20 V Coss 1 Crss f = 1 MHz VGS = 0 V 2 0.1 0 0 20 40 0.05 0.1 60 1 10 30 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) Figure 7. Gate Charge Characteristics Figure 8. Capacitance vs Drain to Source Voltage 150 30 10 ID, DRAIN CURRENT (A) IAS, AVALANCHE CURRENT (A) o RθJC = 3 C/W TJ = 25 oC TJ = 100 oC TJ = 125 oC VGS = 10 V 100 VGS = 4.
PAGE 5
2 NORMALIZED THERMAL IMPEDANCE, ZθJA 1 0.1 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 0.01 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA SINGLE PULSE o RθJA = 125 C/W 1E-3 -3 10 -2 10 -1 0 10 10 1 10 100 1000 t, RECTANGULAR PULSE DURATION (sec) Figure 13. Junction-to-Ambient Transient Thermal Response Curve ©2012 Fairchild Semiconductor Corporation FDMC7660 Rev.C5 5 www.fairchildsemi.
PAGE 6
FDMC7660 N-Channel PowerTrench® MOSFET Dimensional Outline and Pad Layout ©2012 Fairchild Semiconductor Corporation FDMC7660 Rev.C5 6 www.fairchildsemi.
PAGE 7
tm tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.