Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFDMC7664, MOSFET

June 2014

FDMC7664 Rev.C4

www.fairchildsemi.com

FDMC7664 N-Channel PowerTrench

MOSFET

FDMC7664

N-Channel PowerTrench

MOSFET

30 V, 18.8 A, 4.2 mΩ

Features

 Max r

DS(on)

= 4.2 mΩ at V

= 10 V, I

= 18.8 A

 Max r

DS(on)

= 5.5 mΩ at V

= 4.5 V, I

= 16.1 A

 High performance technology for extremely low r

DS(on)

 Termination is Lead-free and RoHS Compliant

General Description

This N-Channel MOSFET is produced using Fairchild

Semiconductor’s advanced Power

Trench

process that has

been especially tailored to minimize the on-state resistance.

This

device is well suited for Power Management and load switching

applications common in Notebook Computers and Portable

Battery Packs.

Applications

 DC - DC Buck Converters

 Notebook battery power management

 Load switch in Notebook

Top

MLP 3.3x3.3

Bottom

Pin 1

MOSFET Maximum Ratings T

= 25 °C unless otherwise noted

Thermal Characteristics

Package Marking and Ordering Information

Symbol Parameter Ratings Units

Drain to Source Voltage 30 V

Gate to Source Voltage ±20 V

Drain Current -Continuous T

= 25 °C 24

A -Continuous T

= 25 °C (Note 1a) 18.8

-Pulsed 60

Single Pulse Avalanche Energy (Note 3) 188 mJ

Power Dissipation T

= 25 °C 45

Power Dissipation T

= 25 °C (Note 1a) 2.3

, T

STG

Operating and Storage Junction Temperature Range -55 to +150 °C

θJC

Thermal Resistance, Junction to Case 2.8

°C/W

θJA

Thermal Resistance, Junction to Ambient (Note 1a) 53

Device Marking Device Package Reel Size Tape Width Quantity

FDMC7664 FDMC7664 MLP 3.3x3.3 13 ’’ 12 mm 3000 units

Summary of content (7 pages)

PAGE 1
FDMC7664 N-Channel PowerTrench® MOSFET 30 V, 18.8 A, 4.2 mΩ Features General Description This N-Channel MOSFET is produced using Fairchild Semiconductor’s advanced Power Trench® process that has been especially tailored to minimize the on-state resistance. This device is well suited for Power Management and load switching applications common in Notebook Computers and Portable Battery Packs. Max rDS(on) = 4.2 mΩ at VGS = 10 V, ID = 18.8 A Max rDS(on) = 5.5 mΩ at VGS = 4.5 V, ID = 16.
PAGE 2
Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V ΔBVDSS ΔTJ Breakdown Voltage Temperature Coefficient ID = 250 μA, referenced to 25 °C IDSS Zero Gate Voltage Drain Current IGSS Gate to Source Leakage Current, Forward 30 V 12 VDS = 24 V, VGS = 0 V mV/°C 1 TJ = 125 °C μA 250 VGS = 20 V, VDS = 0 V 100 nA 3.
PAGE 3
5 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 60 VGS = 10 V VGS = 6 V VGS = 4.5 V VGS = 4 V ID, DRAIN CURRENT (A) 45 VGS = 3.5 V 30 VGS = 3 V 15 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 0 0.0 0.3 0.6 0.9 VGS = 3 V 4 3 VGS = 4 V 1 VGS = 10 V VGS = 6 V 0 1.2 0 Figure 1. On Region Characteristics 15 30 ID, DRAIN CURRENT (A) 45 60 Figure 2. Normalized On-Resistance vs. Drain Current and Gate Voltage 12 ID = 18.8 A VGS = 10 V rDS(on), DRAIN TO 1.4 1.2 1.0 0.8 0.
PAGE 4
7000 Ciss ID = 18.8 A 8 VDD = 10 V CAPACITANCE (pF) VGS, GATE TO SOURCE VOLTAGE (V) 10 VDD = 15 V 6 VDD = 20 V 4 Coss 1000 Crss 2 100 0 0 15 30 45 f = 1 MHz VGS = 0 V 50 0.1 60 Figure 7. Gate Charge Characteristics 30 90 80 ID, DRAIN CURRENT (A) IAS, AVALANCHE CURRENT (A) 10 Figure 8. Capacitance vs. Drain to Source Voltage 30 10 TJ = 25 oC TJ = 100 oC TJ = 125 oC 70 60 VGS = 10 V 50 40 VGS = 4.5 V 30 20 10 1 0.01 0.
PAGE 5
NORMALIZED THERMAL IMPEDANCE, ZθJA 2 1 0.1 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 0.01 t2 SINGLE PULSE NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA o RθJA = 125 C/W 0.001 0.0005 -4 10 (Note 1b) -3 10 -2 10 -1 10 1 10 100 1000 t, RECTANGULAR PULSE DURATION (sec) Figure 13. Junction-to-Ambient Transient Thermal Response Curve ©2009 Fairchild Semiconductor Corporation FDMC7664 Rev.C4 5 www.fairchildsemi.
PAGE 6
FDMC7664 N-Channel PowerTrench® MOSFET Dimensional Outline and Pad Layout Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
PAGE 7
tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.