Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFDMC7692S, MOSFET

FDMC7692S N-Channel PowerTrench

SyncFET

FDMC7692S Rev.C4

www.fairchildsemi.com

June 2014

FDMC7692S

N-Channel PowerTrench

SyncFET

30 V, 18 A, 9.3 mΩ

Features

 Max r

DS(on)

= 9.3 mΩ at V

= 10 V, I

= 12.5 A

 Max r

DS(on)

= 13.6 mΩ at V

= 4.5 V, I

= 10.4 A

 High performance technology fo

r extremely low r

DS(on)

 Termination is Lead-free and RoHS Compliant

General Description

This FDMC7692S is produced using Fairchild Semiconductor’s

advanced PowerTrench

process that has been especially

tailored to minimize the on-state resistance. This device is well

suited for Power Management and load switching applications

common in Notebook Computers and Portable Battery packs.

Applications

 DC - DC Buck Converters

 Notebook DC - DC application

MOSFET Maximum Ratings T

= 25 °C unless otherwise noted

Thermal Characteristics

Package Marking and Ordering Information

Symbol Parameter Ratings Units

Drain to Source Voltage 30 V

Gate to Source Voltage ±20 V

Drain Current -Continuous T

= 25 °C 18

A -Continuous T

= 25 °C (Note 1a) 12.5

-Pulsed 45

Sinlge Pulse Avalanche Energy (Note 3) 21 mJ

Power Dissipation T

= 25 °C 27

Power Dissipation T

= 25 °C (Note 1a) 2.3

, T

STG

Operating and Storage Junction Temperature Range -55 to +150 °C

θJC

Thermal Resistance, Junction to Case 4.7 °C/W

θJA

Thermal Resistance, Junction to Ambient (Note 1a) 53 °C/W

Device Marking Device Package Reel Size Tape Width Quantity

FDMC7692S FDMC7692S MLP 3.3X3.3 13 ’’ 12 mm 3000 units

MLP 3.3x3.3

Bottom

Top

Pin 1

Summary of content (10 pages)

PAGE 1
FDMC7692S N-Channel PowerTrench® SyncFETTM 30 V, 18 A, 9.3 mΩ Features General Description Max rDS(on) = 9.3 mΩ at VGS = 10 V, ID = 12.5 A This FDMC7692S is produced using Fairchild Semiconductor’s advanced PowerTrench® process that has been especially tailored to minimize the on-state resistance. This device is well suited for Power Management and load switching applications common in Notebook Computers and Portable Battery packs. Max rDS(on) = 13.6 mΩ at VGS = 4.5 V, ID = 10.
PAGE 2
Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = 1 mA, VGS = 0 V ΔBVDSS ΔTJ Breakdown Voltage Temperature Coefficient 30 V ID = 10 mA, referenced to 25 °C IDSS Zero Gate Voltage Drain Current VDS = 24 V, VGS = 0 V 500 μA IGSS Gate to Source Leakage Current VGS = 20 V, VDS = 0 V 100 nA 3.
PAGE 3
45 ID, DRAIN CURRENT (A) 36 VGS = 6 V VGS = 4.5 V 27 VGS = 4 V 18 VGS = 3.5 V 9 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 0 0 0.2 0.4 0.6 0.8 3.5 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE VGS = 10 V PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 3.0 VGS = 3.5 V 2.5 VGS = 4 V 2.0 VGS = 4.5 V 1.5 VGS = 6 V 1.0 VGS = 10 V 0.5 1.0 0 9 18 VDS, DRAIN TO SOURCE VOLTAGE (V) 1.6 45 40 ID = 12.5 A VGS = 10 V rDS(on), DRAIN TO 1.4 1.2 1.0 0.8 0.
PAGE 4
VGS, GATE TO SOURCE VOLTAGE (V) 10 3000 IDSS = 12.5 A VDD = 10 V 8 CAPACITANCE (pF) 1000 VDD = 15 V 6 VDD = 20 V 4 2 Ciss Coss 100 Crss f = 1 MHz VGS = 0 V 0 0 3 6 9 12 15 10 0.1 18 1 Qg, GATE CHARGE (nC) Figure 7. Gate Charge Characteristics Figure 8. Capacitance vs Drain to Source Voltage 20 100 10 ID, DRAIN CURRENT (A) IAS, AVALANCHE CURRENT (A) 30 10 VDS, DRAIN TO SOURCE VOLTAGE (V) TJ = 25 oC TJ = 100 oC TJ = 125 oC 10 100 us 1ms 1 0.
PAGE 5
r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 2 1 0.1 0.01 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 SINGLE PULSE NOTES: ZθJA(t) = r(t) x RθJA 0.001 0.0001 -4 10 RθJA = 125 °C/W Peak TJ = PDM x ZθJA(t) + TA Duty Cycle, D = t1 / t2 -3 10 -2 10 -1 10 1 10 100 1000 t, RECTANGULAR PULSE DURATION (sec) Figure 12. Junction-to-Ambient Transient Thermal Response Curve ©2010 Fairchild Semiconductor Corporation FDMC7692S Rev.C4 5 www.fairchildsemi.
PAGE 6
SyncFET Schottky body diode Characteristics Fairchild’s SyncFET process embeds a Schottky diode in parallel with PowerTrench MOSFET. This diode exhibits similar characteristics to a discrete external Schottky diode in parallel with a MOSFET. Figure 13 shows the reverse recovery characteristic of the FDMC7692S. Schottky barrier diodes exhibit significant leakage at high temperature and high reverse voltage. This will increase the power in the device.
PAGE 7
A 0.10 C 2X B 8 (3.40) 2.37 5 0.45(4X) 2.15 (1.70) (0.40) KEEP OUT AREA (0.65) PIN1 IDENT A 0.10 C TOP VIEW 0.65 2X 1 4 0.42(8X) 1.95 0.8 MAX RECOMMENDED LAND PATTERN 0.10 C (0.20) 0.08 C 0.70(4X) 0.05 0.00 SIDE VIEW C SEATING PLANE 2.27+0.05 1 4 0.45+0.05 (4X) (0.40) (1.20) 2.05+0.05 0.45+0.05 (3X) NOTES: A. EXCEPT AS NOTED, PACKAGE CONFORMS TO JEDEC REGISTRATION MO-240 VARIATION BA.. B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. D.
PAGE 8
3.30 0.05 C B A 2X 3.30 0.05 C A B 2X 3.30 3.30 PIN#1 IDENT 0.05 C TOP VIEW 2X PIN#1 IDENT TOP VIEW 0.05 C 2X 0.10 C 3.20 0.08 C SIDE VIEW SEATING PLANE PIN #1 IDENT C SIDE VIEW (0.50)4X (0.79) 1 4 OPTIONAL TIE BARS MAY APPEAR IN THESE AREAS 1 OPTIONAL - DRAFT ANGLE MAY APPEAR ON ALL 4 SIDES OF THE PACKAGE 4 (0.40) (0.35) (1.15) 3.00 R0.15 8 8 0.65 5 0.10 0.05 1.
PAGE 9
3.30 0.05 C B A 2X 8 (3.40) 2.37 5 0.45(4X) 2.15 (1.70) 3.30 (0.40) KEEP OUT AREA (0.65) 0.70(4X) PIN#1 IDENT 0.05 C TOP VIEW 0.65 2X 1 4 0.42(8X) 1.95 RECOMMENDED LAND PATTERN 0.10 C 0.08 C NOTES: C SIDE VIEW SEATING PLANE A. DOES NOT CONFORM TO JEDEC REGISTRATION MO-229 B. DIMENSIONS ARE IN MILLIMETERS. 2.27+0.05 PIN #1 IDENT (0.50)4X (0.79) 1 C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 2009. D. LAND PATTERN RECOMMENDATION IS EXISTING INDUSTRY LAND PATTERN. 4 E.
PAGE 10
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