Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFDMC8010, MOSFET

April 2014

FDMC8010 Rev.C1

www.fairchildsemi.com

FDMC8010 N-Channel PowerTrench

MOSFET

FDMC8010

N-Channel PowerTrench

MOSFET

30 V, 75 A, 1.3 mΩ

Features

 Max r

DS(on)

= 1.3 mΩ at V

= 10 V, I

= 30 A

 Max r

DS(on)

= 1.8 mΩ at V

= 4.5 V, I

= 25 A

 High performance technology for extremely low r

DS(on)

 Termination is Lead-free and RoHS Compliant

General Description

This N-Channel MOSFET is produced using Fairchild

Semiconductor’s advanced PowerTrench

process that has

been especially tailored to minimize the on-state resistance. This

device is well suited for applications where ultra low

DS(on)

required in small spaces such as High performance VRM, POL

and Oring functions.

Applications

 DC - DC Buck Converters

 Point of Load

 High Efficiency Load Switch and Low Side Switching

 Oring FET

MOSFET Maximum Ratings T

= 25 °C unless otherwise noted

Thermal Characteristics

Package Marking and Ordering Information

Symbol Parameter Ratings Units

Drain to Source Voltage 30 V

Gate to Source Volage (Note 4) ±20 V

Drain Current -Continuous (Package limited) T

= 25 °C 75

-Continuous (Silicon limited) T

= 25 °C 166

-Continuous T

= 25 °C (Note 1a) 30

-Pulsed 120

Single Pulse Avalance Energy (Note 3) 153 mJ

Power Dissipation T

= 25 °C 54

Power Dissipation T

= 25 °C (Note 1a) 2.4

, T

STG

Operating and Storage Junction Temperature Range -55 to +150 °C

θJC

Thermal Resistance, Junction to Case 2.3

°C/W

θJA

Thermal Resistance, Junction to Ambient (Note 1a) 53

Device Marking Device Package Reel Size Tape Width Quantity

FDMC8010 FDMC8010 Power 33 13 ’’ 12

mm 3000 units

BottomTop

Power 33

Pin 1

Summary of content (7 pages)

PAGE 1
FDMC8010 N-Channel PowerTrench® MOSFET 30 V, 75 A, 1.3 mΩ Features General Description This N-Channel MOSFET is produced using Fairchild Semiconductor’s advanced PowerTrench® process that has been especially tailored to minimize the on-state resistance. This device is well suited for applications where ultra low rDS(on) is required in small spaces such as High performance VRM, POL and Oring functions. Max rDS(on) = 1.3 mΩ at VGS = 10 V, ID = 30 A Max rDS(on) = 1.8 mΩ at VGS = 4.
PAGE 2
Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = 1 mA, VGS = 0 V ΔBVDSS ΔTJ Breakdown Voltage Temperature Coefficient 30 V ID = 1 mA, referenced to 25 °C IDSS Zero Gate Voltage Drain Current VDS = 24 V, VGS = 0 V 1 μA IGSS Gate to Source Leakage Current VGS = 20 V, VDS = 0 V 100 nA 2.
PAGE 3
120 5 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE VGS = 10 V ID, DRAIN CURRENT (A) VGS = 4.5 V VGS = 4 V 80 VGS = 3.5 V 40 VGS = 3 V 0 0.0 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 0.2 0.4 4 VGS = 3 V 3 0 0.6 0 40 rDS(on), DRAIN TO SOURCE ON-RESISTANCE (mΩ) NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 0.8 IS, REVERSE DRAIN CURRENT (A) VDS = 5 V TJ = 150 oC TJ = 25 oC 40 TJ = -55 oC 2.0 2.5 1 TJ = 25 oC 2 200 100 10 4 6 8 10 VGS = 0 V TJ = 150 oC 1 TJ = 25 oC 0.
PAGE 4
10000 ID = 30 A Ciss VDD = 12 V 8 CAPACITANCE (pF) VGS, GATE TO SOURCE VOLTAGE (V) 10 VDD = 15 V 6 VDD = 18 V 4 Coss 1000 Crss 2 0 f = 1 MHz VGS = 0 V 0 20 40 60 100 0.1 80 1 10 30 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) Figure 7. Gate Charge Characteristics Figure 8. Capacitance vs Drain to Source Voltage 200 100 o TJ = 25 oC ID, DRAIN CURRENT (A) IAS, AVALANCHE CURRENT (A) RθJC = 2.3 C/W VGS = 10 V 150 TJ = 100 oC 100 10 TJ 1 0.001 0.01 = 125 oC 0.
PAGE 5
NORMALIZED THERMAL IMPEDANCE, ZθJA 2 1 0.1 0.01 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 0.0001 -4 10 t2 SINGLE PULSE 0.001 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA o RθJA = 125 C/W -3 10 -2 10 -1 10 1 10 100 1000 t, RECTANGULAR PULSE DURATION (sec) Figure 13. Junction-to-Ambient Transient Thermal Response Curve ©2011 Fairchild Semiconductor Corporation FDMC8010 Rev.C1 5 www.fairchildsemi.
PAGE 6
FDMC8010 N-Channel PowerTrench® MOSFET Dimensional Outline and Pad Layout Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
PAGE 7
tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.