Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFDMC8200, MOSFET

June 2014

FDMC8200 Dual N-Channel PowerTrench

MOSFET

FDMC8200 Rev.A2

FDMC8200

Dual N-Channel PowerTrench

MOSFET

30 V, 9.5 mΩ and 20 mΩ

Features

Q1: N-Channel

 Max r

DS(on)

= 20 mΩ at V

= 10 V, I

= 6 A

 Max r

DS(on)

= 32 mΩ at V

= 4.5 V, I

= 5 A

Q2: N-Channel

 Max r

DS(on)

= 9.5 mΩ at V

= 10 V, I

= 9 A

 Max r

DS(on)

= 13.5 mΩ at V

= 4.5 V, I

= 7 A

 RoHS Compliant

General Description

This device includes two specialized N-Channel MOSFETs in a

dual Power33 (3mm x 3mm MLP) package. The switch node

has been internally connected to enable easy placement and

routing of synchronous buck converters. The control

MOSFET (Q1) and synchronous MOSFET (Q2) have been

designed to provide optimal power efficiency.

Applications

 Mobile Computing

 Mobile Internet Devices

 General Purpose Point of Load

MOSFET Maximum Ratings T

= 25 °C unless otherwise noted

Thermal Characteristics

Package Marking and Ordering Information

Symbol Parameter Q1 Q2 Units

Drain to Source Voltage 30 30 V

Gate to Source Voltage (Note 3) ±20 ±20 V

Drain Current - Continuous (Package limited) T

= 25 °C 18 18

- Continuous (Silicon limited) T

= 25 °C 23 45

- Continuous T

= 25 °C 8

- Pulsed 40 40

Power Dissipation T

= 25 °C 1.9

2.2

Power Dissipation T

= 25 °C 0.7

0.9

, T

STG

Operating and Storage Junction Temperature Range -55 to +150 °C

θJA

Thermal Resistance, Junction to Ambient 65

°C/WR

θJA

Thermal Resistance, Junction to Ambient 180

145

θJC

Thermal Resistance, Junction to Case 7.5 4

Device Marking Device Package Reel Size Tape Width Quantity

FDMC8200 FDMC8200 Power 33 13 ” 12 mm 3000 units

BOTTOM

D2/S1

Pin 1

Power 33

BOTTOM

Summary of content (11 pages)

PAGE 1
FDMC8200 Dual N-Channel PowerTrench® MOSFET 30 V, 9.5 mΩ and 20 mΩ Features General Description Q1: N-Channel This device includes two specialized N-Channel MOSFETs in a Max rDS(on) = 20 mΩ at VGS = 10 V, ID = 6 A dual Power33 (3mm x 3mm MLP) package. The switch node has been internally connected to enable easy placement and Max rDS(on) = 32 mΩ at VGS = 4.5 V, ID = 5 A routing of synchronous buck converters.
PAGE 2
Symbol Parameter Test Conditions Type Min 30 30 Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V ID = 250 μA, VGS = 0 V Q1 Q2 ΔBVDSS ΔTJ Breakdown Voltage Temperature Coefficient ID = 250 μA, referenced to 25 °C ID = 250 μA, referenced to 25 °C Q1 Q2 IDSS Zero Gate Voltage Drain Current VDS = 24 V, VGS = 0 V VDS = 24 V, VGS = 0 V Q1 Q2 1 1 μA IGSS Gate to Source Leakage Current VDS = 20 V, VGS = 0 V Q1 Q2 100 100 nA nA 3.0 3.
PAGE 3
Symbol Parameter Test Conditions Type Min Typ Max Units Q1 Q2 0.8 0.8 1.2 1.2 V Q1 Q2 13 21 24 34 ns Q1 Q2 2.3 5.6 10 12 nC Drain-Source Diode Characteristics VSD Source to Drain Diode Forward Voltage VGS = 0 V, IS = 6 A VGS = 0 V, IS = 9 A trr Reverse Recovery Time Qrr Reverse Recovery Charge Q1 IF = 6 A, di/dt = 100 A/s Q2 IF = 9 A, di/dt = 100 A/s (Note 2) (Note 2) Notes: 1. RθJA is determined with the device mounted on a 1in2 pad 2 oz copper pad on a 1.5 x 1.5 in.
PAGE 4
0 4 ID, DRAIN CURRENT (A) VGS = 6 V 30 VGS = 4.5 V 20 VGS = 4 V 10 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX VGS = 3.5 V 0 0.0 0.5 1.0 1.5 2.0 2.5 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX NORMALIZED DRAIN TO SOURCE ON-RESISTANCE VGS = 10 V 3 VGS = 3.5 V VGS = 4 V 2 VGS = 4.5 V 1 0 3.0 0 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 30 40 Figure 2. Normalized On-Resistance vs Drain Current and Gate Voltage 1.6 100 ID = 6 A VGS = 10 V rDS(on), DRAIN TO 1.4 1.2 1.0 0.
PAGE 5
10 1000 VGS, GATE TO SOURCE VOLTAGE (V) ID = 6 A Ciss CAPACITANCE (pF) 8 VDD = 20 V VDD = 15 V 6 VDD = 10 V 4 Coss 100 Crss 2 f = 1 MHz VGS = 0 V 0 0 2 4 6 10 0.1 8 1 10 30 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) Figure 7. Gate Charge Characteristics Figure 8. Capacitance vs Drain to Source Voltage 100 25 o 10 ID, DRAIN CURRENT (A) I D , DRAIN CURRENT (A) RθJC = 7.5 C/W 100 us 1 ms 1 10 ms 100 ms THIS AREA IS LIMITED BY rDS(on) 0.
PAGE 6
2 NORMALIZED THERMAL IMPEDANCE, ZθJA 1 0.1 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA SINGLE PULSE 0.01 o RθJA = 180 C/W 0.003 -4 10 -3 10 -2 10 -1 10 1 10 100 1000 t, RECTANGULAR PULSE DURATION (sec) Figure 12. Junction-to-Ambient Transient Thermal Response Curve ©2009 Fairchild Semiconductor Corporation FDMC8200 Rev.A2 6 www.fairchildsemi.
PAGE 7
40 6 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE ID, DRAIN CURRENT (A) VGS = 10 V 30 VGS = 4.5 V VGS = 4 V 20 VGS = 3.5 V 10 0 0.0 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX VGS = 3 V 0.5 1.0 1.5 2.0 2.5 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 5 VGS = 3 V 4 VGS = 3.5 V 3 VGS = 4 V 2 1 VGS = 10 V 0 3.0 0 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 30 40 Figure 14. Normalized on-Resistance vs Drain Current and Gate Voltage 1.6 60 ID = 9 A VGS = 10 V rDS(on), DRAIN TO 1.4 1.2 1.
PAGE 8
2000 Ciss ID = 9 A 1000 8 VDD = 15 V CAPACITANCE (pF) VGS, GATE TO SOURCE VOLTAGE (V) 10 6 VDD = 10 V VDD = 20 V 4 Coss 100 Crss 2 f = 1 MHz VGS = 0 V 0 0 3 6 9 12 15 10 0.1 18 1 10 30 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) Figure 19. Gate Charge Characteristics Figure 20.
PAGE 9
2 NORMALIZED THERMAL IMPEDANCE, ZθJA 1 0.1 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 0.01 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA SINGLE PULSE o RθJA = 145 C/W 0.001 -4 10 -3 10 -2 10 -1 10 1 10 100 1000 t, RECTANGULAR PULSE DURATION (sec) Figure 23. Junction-to-Ambient Transient Thermal Response Curve ©2009 Fairchild Semiconductor Corporation FDMC8200 Rev.A2 9 www.fairchildsemi.
PAGE 10
FDMC8200 Dual N-Channel PowerTrench® MOSFET Dimensional Outline and Pad Layout Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
PAGE 11
tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.