Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFDMC8200S, MOSFET

March 2011

FDMC8200S Dual N-Channel PowerTrench

MOSFET

FDMC8200S Rev.C4

FDMC8200S

Dual N-Channel PowerTrench

MOSFET

30 V, 10 mΩ, 20 mΩ

Features

Q1: N-Channel

 Max r

DS(on)

= 20 mΩ at V

= 10 V, I

= 6 A

 Max r

DS(on)

= 32 mΩ at V

= 4.5 V, I

= 5 A

Q2: N-Channel

 Max r

DS(on)

= 10 mΩ at V

= 10 V, I

= 8.5 A

 Max r

DS(on)

= 13.5 mΩ at V

= 4.5 V, I

= 7.2 A

 RoHS Compliant

General Description

This device includes two specialized N-Channel MOSFETs in a

due power33(3mm X 3mm MLP) package. The switch node has

been internally connected to enable easy placement and routing

of synchronous buck converters. The control MOSFET (Q1) and

synchronous MOSFET (Q2) have been designed to provide

optimal power efficiency.

Applications

 Mobile Computing

 Mobile Internet Devices

 General Purpose Point of Load

Bottom

Power33

Pin 1

GND

Q 1

Q 2

MOSFET Maximum Ratings T

= 25°C unless otherwise noted

Thermal Characteristics

Package Marking and Ordering Information

Symbol Parameter Q1 Q2 Units

Drain to Source Voltage 30 30 V

Gate to Source Voltage (Note 4) ±20 ±20 V

Drain Current -Continuous (Package limited) T

= 25 °C 18 13

-Continuous (Silicon limited) T

= 25 °C 23 46

-Continuous T

= 25 °C 6

8.5

-Pulsed 40 27

Single Pulse Avalanche Energy (Note 3) 12 32

Power Dissipation for Single Operation T

= 25°C 1.9

2.5

Power Dissipation for Single Operation T

= 25°C 0.7

1.0

, T

STG

Operating and Storage Junction Temperature Range -55 to +150 °C

θJA

Thermal Resistance, Junction to Ambient 65

°C/WR

θJA

Thermal Resistance, Junction to Ambient 180

125

θJC

Thermal Resistance, Junction to Case 7.5 4.2

Device Marking Device Package Reel Size Tape Width Quantity

FDMC8200S FDMC8200S Power 33 13” 12

mm 3000 units

Summary of content (12 pages)

PAGE 1
FDMC8200S Dual N-Channel PowerTrench® MOSFET 30 V, 10 mΩ, 20 mΩ Features General Description Q1: N-Channel Q2: N-Channel This device includes two specialized N-Channel MOSFETs in a due power33(3mm X 3mm MLP) package. The switch node has been internally connected to enable easy placement and routing of synchronous buck converters. The control MOSFET (Q1) and synchronous MOSFET (Q2) have been designed to provide optimal power efficiency. Max rDS(on) = 10 mΩ at VGS = 10 V, ID = 8.
PAGE 2
Symbol Parameter Test Conditions Type Min 30 30 Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V ID = 1mA, VGS = 0 V Q1 Q2 ΔBVDSS ΔTJ Breakdown Voltage Temperature Coefficient ID = 250 μA, referenced to 25°C ID = 1mA, referenced to 25°C Q1 Q2 IDSS Zero Gate Voltage Drain Current VDS = 24 V, VGS = 0 V Q1 Q2 1 500 μA IGSS Gate to Source Leakage Current VGS = ±20 V, VDS = 0 V Q1 Q2 100 100 nA nA 3.0 3.
PAGE 3
Symbol Parameter Test Conditions Type Min Typ Max Units Q1 Q2 Q2 0.8 0.8 0.6 1.2 1.2 0.8 V Q1 Q2 13 20 24 32 ns Q1 Q2 2.3 15 10 24 nC Drain-Source Diode Characteristics VSD VGS = 0 V, IS = 6 A Source-Drain Diode Forward Voltage VGS = 0 V, IS = 8.5 A VGS = 0 V, IS = 1.3 A trr Reverse Recovery Time Qrr Reverse Recovery Charge (Note 2) (Note 2) (Note 2) Q1 IF = 6 A, di/dt = 100 A/s Q2 IF = 8.5 A, di/dt = 300 A/s Notes: 1.
PAGE 4
40 ID, DRAIN CURRENT (A) VGS = 6 V 30 VGS = 4.5 V 20 VGS = 4 V 10 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX VGS = 3.5 V 0 0.0 0.5 1.0 1.5 2.0 2.5 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX NORMALIZED DRAIN TO SOURCE ON-RESISTANCE VGS = 10 V 3 VGS = 3.5 V VGS = 4 V 2 VGS = 4.5 V 1 0 0 3.0 10 Figure 1. On Region Characteristics 30 40 Figure 2. Normalized On-Resistance vs Drain Current and Gate Voltage 100 1.
PAGE 5
1000 ID = 6 A Ciss 8 CAPACITANCE (pF) VGS, GATE TO SOURCE VOLTAGE (V) 10 VDD = 20 V VDD = 15 V 6 VDD = 10 V 4 Coss 100 Crss 2 f = 1 MHz VGS = 0 V 0 0 2 4 6 10 0.1 8 1 30 Figure 8. Capacitance vs Drain to Source Voltage 25 8 7 6 5 o RθJC = 7.5 C/W ID, DRAIN CURRENT (A) IAS, AVALANCHE CURRENT (A) Figure 7. Gate Charge Characteristics 4 TJ = 25 oC 3 TJ = 100 oC 2 TJ = 125 oC 1 0.01 0.1 1 20 VGS = 10 V 15 Limited by Package 10 VGS = 4.
PAGE 6
2 NORMALIZED THERMAL IMPEDANCE, ZθJA 1 0.1 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC x RθJc + TC SINGLE PULSE 0.01 o RθJA = 180 C/W 0.003 -4 10 -3 10 -2 10 -1 10 1 10 100 1000 t, RECTANGULAR PULSE DURATION (sec) Figure 13. Junction-to-Ambient Transient Thermal Response Curve ©2011 Fairchild Semiconductor Corporation FDMC8200S Rev.C4 6 www.fairchildsemi.
PAGE 7
4 VGS = 10 V VGS = 4.5 V VGS = 4 V VGS = 3.5 V 18 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE ID, DRAIN CURRENT (A) 27 VGS = 3 V 9 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 0 0.0 0.5 1.0 3 VGS = 3.5 V 2 VGS = 4 V 1 1.5 0 9 18 27 ID, DRAIN CURRENT (A) Figure 14. On- Region Characteristics Figure 15. Normalized on-Resistance vs Drain Current and Gate Voltage 1.6 100 ID = 8.5 A VGS = 10 V rDS(on), DRAIN TO 1.4 1.2 1.0 0.
PAGE 8
3000 ID = 8.5 A 1000 8 VDD = 15 V CAPACITANCE (pF) VGS, GATE TO SOURCE VOLTAGE (V) 10 6 VDD = 10 V VDD = 20 V 4 Ciss Coss 100 2 f = 1 MHz VGS = 0 V 10 0.1 0 0 2 4 6 8 10 12 14 16 10 30 Figure 21. Capacitance vs Drain to Source Voltage Figure 20. Gate Charge Characteristics 15 ID, DRAIN CURRENT (A) 20 IAS, AVALANCHE CURRENT (A) 1 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) 10 TJ = 25 oC TJ = 100 oC TJ = 125 oC 12 VGS = 10 V 9 VGS = 4.
PAGE 9
2 NORMALIZED THERMAL IMPEDANCE, ZθJA 1 0.1 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 0.01 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC x RθJC + TC SINGLE PULSE o RθJA = 125 C/W (Note 1b) 0.001 -4 10 -3 10 -2 10 -1 10 1 10 100 1000 t, RECTANGULAR PULSE DURATION (sec) Figure 26. Junction-to-Ambient Transient Thermal Response Curve ©2011 Fairchild Semiconductor Corporation FDMC8200S Rev.C4 9 www.fairchildsemi.
PAGE 10
SyncFET Schottky body diode Characteristics Schottky barrier diodes exhibit significant leakage at high temperature and high reverse voltage. This will increase the power in the device. Fairchild’s SyncFET process embeds a Schottky diode in parallel with PowerTrench MOSFET. This diode exhibits similar characteristics to a discrete external Schottky diode in parallel with a MOSFET. Figure 14 shows the reverses recovery characteristic of the FDMC8200S. 7 IDSS, REVERSE LEAKAGE CURRENT (A) 0.
PAGE 11
FDMC8200S Dual N-Channel PowerTrench® MOSFET Dimensional Outline and Pad Layout ©2011 Fairchild Semiconductor Corporation FDMC8200S Rev.C4 11 www.fairchildsemi.
PAGE 12
tm tm tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.