Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFDMC8321L, MOSFET

February 2013

FDMC8321L Rev.C2

www.fairchildsemi.com

FDMC8321L N-Channel PowerTrench

MOSFET

FDMC8321L

N-Channel Power Trench

MOSFET

40 V, 49 A, 2.5 mΩ

Features

 Max r

DS(on)

= 2.5 mΩ at V

= 10 V, I

= 22 A

 Max r

DS(on)

= 4.1 mΩ at V

= 4.5 V, I

= 18 A

 Advanced Package and Silicon combination for low r

DS(on)

and hign efficiency

 Next Generation enhanced body diode technology,

engineered for soft recovery

 100% UIL tested

 RoHS Compliant

General Description

This N-Channel MOSFET has been designed specifically to

improve the overall efficiency and to minimize switch node

ringing of DC/DC converters using either synchronous or

convertional switching PWM contollers. It has been optimized for

low gate charge, low

DS(on)

, fast switching speed body diode

reverse recovery performance.

Applications

 Synchronous rectifier

 Load switch/Orring

 Motor switch

Top

Power 33

Bottom

Pin 1

MOSFET Maximum Ratings T

= 25 °C unless otherwise noted

Thermal Characteristics

Package Marking and Ordering Information

Symbol Parameter Ratings Units

Drain to Source Voltage 40 V

Gate to Source Voltage ±20 V

Drain Current -Continuous T

= 25 °C 49

A -Continuous T

= 25 °C (Note 1a) 22

-Pulsed 100

Single Pulse Avalanche Energy (Note 3) 86 mJ

Power Dissipation T

= 25 °C 40

Power Dissipation T

= 25 °C (Note 1a) 2.3

, T

STG

Operating and Storage Junction Temperature Range -55 to +150 °C

θJC

Thermal Resistance, Junction to Case (Note 1) 3.1

°C/W

θJA

Thermal Resistance, Junction to Ambient (Note 1a) 53

Device Marking Device Package Reel Size Tape Width Quantity

FDMC8321L FDMC8321L Power33 13 ’’ 12 mm 3000 units

Summary of content (7 pages)

PAGE 1
FDMC8321L N-Channel Power Trench® MOSFET 40 V, 49 A, 2.5 mΩ Features General Description Max rDS(on) = 2.5 mΩ at VGS = 10 V, ID = 22 A This N-Channel MOSFET has been designed specifically to improve the overall efficiency and to minimize switch node ringing of DC/DC converters using either synchronous or convertional switching PWM contollers. It has been optimized for low gate charge, low rDS(on), fast switching speed body diode reverse recovery performance. Max rDS(on) = 4.1 mΩ at VGS = 4.
PAGE 2
Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V ΔBVDSS ΔTJ Breakdown Voltage Temperature Coefficient ID = 250 μA, referenced to 25 °C IDSS Zero Gate Voltage Drain Current VDS = 32 V, VGS = 0 V 1 μA IGSS Gate to Source Leakage Current VGS = ±20 V, VDS = 0 V ±100 nA 3 V 40 V 22 mV/°C On Characteristics VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250 μA ΔVGS(th) ΔTJ Gate to Source
PAGE 3
100 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 6 ID, DRAIN CURRENT (A) VGS = 3.5 V 80 VGS = 10 V VGS = 4.5 V 60 VGS = 4 V 40 VGS = 3 V 20 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 0 0 0.5 1.0 1.5 5 4 VGS = 3.5 V 3 VGS = 4 V 2 1 2.0 0 20 40 60 80 100 ID, DRAIN CURRENT (A) Figure 1. On Region Characteristics Figure 2. Normalized On-Resistance vs Drain Current and Gate Voltage 1.6 10 ID = 22 A VGS = 10 V 1.5 rDS(on), DRAIN TO 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.
PAGE 4
10000 ID = 22 A 8 VDD = 24 V VDD = 16 V Ciss CAPACITANCE (pF) VGS, GATE TO SOURCE VOLTAGE (V) 10 6 VDD = 20 V 4 1000 Coss 100 2 f = 1 MHz VGS = 0 V 0 0 10 20 30 40 50 Figure 7. Gate Charge Characteristics 10 40 Figure 8. Capacitance vs Drain to Source Voltage 100 100 VGS = 10 V ID, DRAIN CURRENT (A) IAS, AVALANCHE CURRENT (A) 1 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) TJ = 25 oC 10 TJ = 100 oC TJ = 125 oC 80 60 VGS = 4.
PAGE 5
2 NORMALIZED THERMAL IMPEDANCE, ZθJA 1 0.1 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 0.01 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA SINGLE PULSE o RθJA = 125 C/W 0.001 -3 10 -2 10 -1 10 1 10 100 1000 t, RECTANGULAR PULSE DURATION (sec) Figure 13. Junction-to-Ambient Transient Thermal Response Curve FDMC8321L Rev.C2 5 www.fairchildsemi.
PAGE 6
FDMC8321L N-Channel PowerTrench® MOSFET Dimensional Outline and Pad Layout FDMC8321L Rev.C2 6 www.fairchildsemi.
PAGE 7
tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.