Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFDMC8327L, MOSFET

October 2013

FDMC8327L N-Channel PowerTrench

MOSFET

FDMC8327L Rev.C2

1234

DDDD

SSS

Bottom

Top

MLP 3.3x3.3

678

FDMC8327L

N-Channel PowerTrench

MOSFET

40 V, 14 A, 9.7 mΩ

Features

 Max r

DS(on)

= 9.7 mΩ at V

= 10 V, I

= 12 A

 Max r

DS(on)

= 12.5 mΩ at V

= 4.5 V, I

= 10 A

 Low Profile - 0.8mm max in Power 33

 100% UIL test

 RoHS Compliant

General Description

This N-Channel MOSFET is produced using Fairchild

Semiconductor’s advanced Power Trench

process that has

been especially tailored to minimize the on-state resistance and

yet maintain superior switching performance.

Application

 DC-DC Conversion

MOSFET Maximum Ratings T

= 25 °C unless otherwise noted

Thermal Characteristics

Package Marking and Ordering Information

Symbol Parameter Ratings Units

Drain to Source Voltage 40 V

Gate to Source Voltage ±20 V

Drain Current - Continuous (Package limited) T

= 25 °C 14

- Continuous (Silicon limited) T

= 25 °C 43

- Continuous T

= 25 °C (Note 1a) 12

- Pulsed 60

Single Pulse Avalanche Energy (Note 3) 25 mJ

Power Dissipation T

= 25 °C 30

Power Dissipation T

= 25 °C (Note 1a) 2.3

, T

STG

Operating and Storage Junction Temperature Range -55 to +150 °C

θJC

Thermal Resistance, Junction to Case (Note 1) 4.2

°C/W

θJA

Thermal Resistance, Junction to Ambient (Note 1a) 53

Device Marking Device Package Reel Size Tape Width Quantity

FDMC8327L FDMC8327L Power 33 13 ” 12 mm 3000 units

Summary of content (8 pages)

PAGE 1
FDMC8327L N-Channel PowerTrench® MOSFET 40 V, 14 A, 9.7 mΩ Features General Description Max rDS(on) = 9.7 mΩ at VGS = 10 V, ID = 12 A This Max rDS(on) = 12.5 mΩ at VGS = 4.5 V, ID = 10 A Semiconductor’s advanced Power Trench® process that has N-Channel MOSFET is produced using Fairchild been especially tailored to minimize the on-state resistance and Low Profile - 0.8mm max in Power 33 yet maintain superior switching performance.
PAGE 2
Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V ΔBVDSS ΔTJ Breakdown Voltage Temperature Coefficient ID = 250 μA, referenced to 25 °C IDSS Zero Gate Voltage Drain Current VDS = 32 V, VGS = 0 V 1 μA IGSS Gate to Source Leakage Current VGS = ±20 V, VDS = 0 V ±100 nA 3.
PAGE 3
4 VGS = 10 V ID, DRAIN CURRENT (A) 50 VGS = 6 V VGS = 4.5 V VGS = 4 V 40 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 60 VGS = 3.5 V 30 20 VGS = 3 V 10 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 0 0.0 0.3 0.6 0.9 1.2 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX VGS = 3 V 3 VGS = 3.5 V 2 VGS = 4 V 1 VGS = 4.5 V 0 1.5 0 Figure 1. On Region Characteristics 30 40 50 60 30 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.
PAGE 4
60 IS, REVERSE DRAIN CURRENT (A) 50 ID, DRAIN CURRENT (A) 100 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX VDS = 5 V 40 TJ = 150 oC 30 TJ = 25 oC 20 10 TJ = -55 oC 0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 VGS = 0 V 10 TJ = 150 oC 1 0.1 TJ = -55 oC 0.01 0.001 0.0 4.5 VGS, GATE TO SOURCE VOLTAGE (V) 0.2 0.4 0.6 0.8 1.0 1.2 VSD, BODY DIODE FORWARD VOLTAGE (V) Figure 5. Transfer Characteristics Figure 6.
PAGE 5
0 ID, DRAIN CURRENT (A) IAS, AVALANCHE CURRENT (A) 20 10 TJ = 25 oC TJ = 100 oC TJ = 125 oC 40 VGS = 10 V 30 VGS = 4.5 V 20 10 Limited by package 1 0.01 0.1 1 10 0 25 30 50 75 100 125 150 o tAV, TIME IN AVALANCHE (ms) TC, CASE TEMPERATURE ( C) Figure 9. Unclamped Inductive Switching Capability Figure 10. Maximum Continuous Drain Current vs Case Temperature 100 300 P(PK), PEAK TRANSIENT POWER (W) ID, DRAIN CURRENT (A) o RθJC = 4.
PAGE 6
2 NORMALIZED THERMAL IMPEDANCE, ZθJA 1 0.1 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 SINGLE PULSE o 0.001 -3 10 t2 RθJA = 125 C/W 0.01 -2 10 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA -1 10 1 10 100 1000 t, RECTANGULAR PULSE DURATION (sec) Figure 13. Junction-to-Ambient Transient Thermal Response Curve ©2012 Fairchild Semiconductor Corporation FDMC8327L Rev.C2 6 www.fairchildsemi.
PAGE 7
A 0.10 C 2X 8 B (3.40) 2.37 5 0.45(4X) 2.15 (1.70) (0.40) KEEP OUT AREA (0.65) PIN1 IDENT A 0.65 0.10 C TOP VIEW 0.70(4X) 1 4 0.42(8X) 1.95 2X 0.8MAX 0.10 C (0.20) 0.08 C 0.05 0.00 SIDE VIEW RECOMMENDED LAND PATTERN C SEATING PLANE 2.27+0.05 1 4 0.45+0.05 (4X) (0.40) (1.20) 2.05+0.05 0.45+0.05 (3X) A 8 0.65 5 1.95 0.32+0.05 (8X) 0.10 0.05 NOTES: A.EXCEPT AS NOTED, PACKAGE CONFORMS TO JEDEC REGISTRATION MO-240 VARIATION BA.. B.DIMENSIONS ARE IN MILLIMETERS. C.
PAGE 8
tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.