Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFDMC8588, MOSFET

June 2012

FDMC8588 Rev.D3

www.fairchildsemi.com

FDMC8588 N-Channel PowerTrench

MOSFET

FDMC8588

N-Channel PowerTrench

MOSFET

25 V, 40 A, 5.7 mΩ

Features

 Max r

DS(on)

= 5.7 mΩ at V

= 4.5 V, I

= 16.5 A

 State-of-the-art switching performance

 Lower output capacitance, gate resistance, and gate charge

boost efficiency

 Shielded gate technology reduces switch node ringing and

increases immunity to EMI and cross conduction

 RoHS Compliant

General Description

This N-Channel MOSFET has been designed specifically to

improve the overall efficiency and to minimize switch node

ringing of DC/DC converters using either synchronous or

conventional switching PWM controllers. It has been optimized

for low gate charge, low r

DS(on)

, fast switching speed and body

diode reverse recovery performance.

Applications

 High side switching for high end computing

 High power density DC-DC synchronous buck converter

Top

Power 33

Bottom

Pin 1

MOSFET Maximum Ratings T

= 25 °C unless otherwise noted

Thermal Characteristics

Package Marking and Ordering Information

Symbol Parameter Ratings Units

Drain to Source Voltage (Note 5) 25 V

Gate to Source Voltage (Note 4) ±12 V

Drain Current - Continuous (Package limited) T

= 25 °C 40

- Continuous (Silicon Limited) T

= 25 °C 59

- Continuous (Note 1a) 16.5

- Pulsed 60

Single Pulse Avalanche Energy (Note 3) 29 mJ

Power Dissipation T

= 25 °C 26

Power Dissipation T

= 25 °C (Note 1a) 2.4

, T

STG

Operating and Storage Junction Temperature Range -55 to +150 °C

θJC

Thermal Resistance, Junction to Case T

= 25 °C 4.7

°C/W

θJA

Thermal Resistance, Junction to Ambient T

= 25 °C (Note 1a) 53

Device Marking Device Package Reel Size Tape Width Quantity

08OD FDMC8588

Power 33

13 ’’ 12 mm 3000 units

Summary of content (7 pages)

PAGE 1
FDMC8588 N-Channel PowerTrench® MOSFET 25 V, 40 A, 5.7 mΩ Features General Description Max rDS(on) = 5.7 mΩ at VGS = 4.5 V, ID = 16.5 A This N-Channel MOSFET has been designed specifically to improve the overall efficiency and to minimize switch node ringing of DC/DC converters using either synchronous or conventional switching PWM controllers. It has been optimized for low gate charge, low rDS(on), fast switching speed and body diode reverse recovery performance.
PAGE 2
Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = 250 μA , VGS = 0 V ΔBVDSS ΔTJ Breakdown Voltage Temperature Coefficient 25 ID = 250 μA , referenced to 25 °C IDSS Zero Gate Voltage Drain Current VDS = 20 V, VGS = 0 V IGSS Gate to Source Leakage Current, Forward VGS = 12 V, VDS = 0 V V 17 mV/°C 1 μA 100 nA 1.
PAGE 3
.0 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 60 VGS = 10 V ID, DRAIN CURRENT (A) 50 VGS = 4.5 V VGS = 4 V 40 VGS = 3 V 30 VGS = 2.5 V 20 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 10 0 0.0 0.2 0.4 0.6 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 2.5 VGS = 2.5 V 2.0 VGS = 4 V 1.5 1.0 VGS = 4.5 V 0.5 0 10 Figure 1. On Region Characteristics rDS(on), DRAIN TO 0.8 SOURCE ON-RESISTANCE (mΩ) NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 1.0 -50 60 PULSE DURATION = 80 μs DUTY CYCLE = 0.
PAGE 4
3000 Ciss ID = 16.5 A 3.6 VDD = 10 V CAPACITANCE (pF) VGS, GATE TO SOURCE VOLTAGE (V) 4.5 VDD = 13 V 2.7 VDD = 15 V 1.8 1000 0.9 Coss Crss 100 f = 1 MHz VGS = 0 V 0.0 0 2 4 6 8 10 30 0.1 12 Figure 7. Gate Charge Characteristics 30 10 ID, DRAIN CURRENT (A) 70 TJ = 25 oC TJ = 100 oC TJ = 125 oC 60 VGS = 10 V 50 40 30 Limited by Package VGS = 4.5 V 20 R = 4.7 oC/W θJC 10 1 0.001 0.01 0.1 1 10 0 25 100 50 tAV, TIME IN AVALANCHE (ms) 125 150 Figure 10.
PAGE 5
2 NORMALIZED THERMAL IMPEDANCE, ZθJA 1 0.1 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 0.01 t2 SINGLE PULSE NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA o RθJA = 125 C/W 1E-3 5E-4 -4 10 -3 10 -2 10 -1 0 10 10 1 10 100 1000 t, RECTANGULAR PULSE DURATION (sec) Figure 13. Junction-to-Ambient Transient Thermal Response Curve ©2012 Fairchild Semiconductor Corporation FDMC8588 Rev.D3 5 www.fairchildsemi.
PAGE 6
3.40 3.20 8 PKG C L 3.40 2.37 MIN A (0.45) 8 B 5 1 2.15 MIN 1.70 3.40 3.20 PKG C L KEEP OUT AREA SYM C L 5 0.70 MIN (0.40) (0.65) 4 1 SEE DETAIL A 4 0.65 0.42 MIN 1.95 LAND PATTERN RECOMMENDATION 0.10 C A B 0.37 0.27 1 PKG C L 1.95 0.65 4 0.50 0.30 (0.20) 2.09 (1.65) 1.89 (0.67) (0.39) 0.52 8 5 NOTES: UNLESS OTHERWISE SPECIFIED A) PACKAGE STANDARD REFERENCE: JEDEC MO-240, ISSUE A, VAR. BA, D ATED OCTOBER 2002. B) ALL D IMENSIONS ARE IN MILLIMETERS.
PAGE 7
tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.